Comments (6)
I'll try it out this weekend and give you any feedback.
from neorv32.
Interesting idea!
Obviously, the hardware flow control signals could be implemented using the GPIO ports and some software overhead. But this overhead might compromise some of the "very high" data throughput.
So having dedicated control signals seems to be a nice solution. I have checked the RTS / CTS specifications and if I got them right
neorv32.uart.RTS_o
(output) would indicate the UART's receiver being ready to receive another byte while neorv32.uart.CTS_i
(input) would indicate the UART's transmitter is allowed to transmit another byte, correct?
Right now I am not sure about the polarity of these signals, but this isn't really a big deal.
Edit
BTW: Nice work on this project! I had it up and running on a Digilent Nexys A7 board quickly without issues.
Thank you very much! 😉
from neorv32.
Yes, that is the way I believe it works: CTS is an input and RTS is an output. I think they are high active signals (at least to the TTL level).
Thanks for considering this enhancement.
from neorv32.
I have added (experimental) RTS/CTS hardware flow control with the last repository update. Since I have no full-scale UART-USB adapter available right now, I could only simulate the flow control so far - but it looks pretty good.
Maybe you can give some feedback if you plan to test the new features. 😉
By the way, RTS and CTS seem to be low-active (they are low-active in the current NEORV32 version).
from neorv32.
It worked great for me on my Nexys A7 board -- RTS/CTS worked as expected.
I'm now running the UART at 460,800 baud, in the bootloader and app code, with no issues.
from neorv32.
I'm glad to hear that! 👍
from neorv32.
Related Issues (20)
- Processor doesn't park itself in a know good state prior to going to sleep HOT 3
- Nexys 4 DDR FPGA board flashing zephyr RTOS hello_world no output on default UART HOT 11
- Atomic accesses documentation error HOT 2
- neorv32_fifo vivado implementation issue HOT 1
- Implementation problem in XILINX ISE HOT 2
- Illegal instruction in coremark HOT 5
- Utilizing on-board SRAM HOT 16
- [idea] Add indirect CSR accesses (Smcsrind ISA extension)? HOT 3
- Illegal compressed instruction reports 2 traps. HOT 7
- Variation in counter values HOT 16
- CSR reads fail for un-implemented features like HPM counters HOT 7
- Cannot upload neorv32_exe.bin for demo CFS on NexysA7 HOT 10
- Reserved compressed instructions do not trigger illegal instruction exception HOT 4
- FPU fflags no being asserted correctly HOT 15
- Instruction to halt TRNG operation HOT 2
- ERR_EXE when uploading neorv32_exe.bin for demo_blink_led on DE2-115 Board HOT 2
- FPU more fflags issues and a few logic bugs HOT 11
- Compressed instruction decoder edge case not handled HOT 3
- hpmevent_cfg_t fails synthesis for hpm_num=0 HOT 5
- c.srli HINT flagged as illegal HOT 5
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from neorv32.