Comments (7)
Hello! Thanks for the information, is perfect start point for try to make it run in those board! I will let you know the results!
from neorv32.
@zipotron, can you please confirm that you are using Alhambra II (HX4K) and not IceZum Alhambra (HX1K)? If so, I suggest you create a PR where:
- Add the constraints file to
setups/osflow/constraints
. - Edit https://github.com/stnolting/neorv32/blob/master/setups/osflow/boards/index.mk and add an
ifeq
block for definingCONSTRAINTS
,PNRFLAGS
(device and package) andIMPL ?= neorv32_$(BOARD)_II_$(ID)
.
We can then iterate on that.
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@umarcor Confirmed! I have the Alhambra II (HX4K), I will start on that ASAP! (In two or three days I guess, depend on my work load)
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PR done, I need help with the ULX3S Makefiles, I don't know why try to take iCE40 VHDL files instead ECP5.
AlhambraII is well done, but fails synthesis, seams something related with the optimization, I can work around with a bit of support
from neorv32.
Looks like the setups have been moved here:
https://github.com/stnolting/neorv32-setups/tree/main/osflow/boards
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Hey there!
first, thanks for this amazing work!
Thank you very much :)
Well, I have at home the board AlhambraII (iCE40) and the ULX3S (ECP5), I am using Yosys with the GHDL plugin. I wanted to synthesize using Yosys and NextPNR for those boards, but couldn't find a start point to do it.
Please, if anyone support me I would like to do those Makefiles.
The documentation of the osflow setups is currently work-in-progress (see #96 and #131).
I am not familiar with the AlhambraII or the ULX3S boards, but the makefiles for iCE40 and ECP5 FPGAs are already there:
You will just need to adapt the pin-mappings:
Then you can run this:
neorv32$ make -C setups/examples BOARD=<fpga_board> <soc>
For example for the ECP5-based OrangeCrab board using a minimal NEORV32 SoC you can do:
neorv32$ make -C setups/examples BOARD=OrangeCrab MinimalBoot
from neorv32.
Right, we sourced-out the FPGA implementations to a new repository.
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Related Issues (20)
- Processor doesn't park itself in a know good state prior to going to sleep HOT 3
- Nexys 4 DDR FPGA board flashing zephyr RTOS hello_world no output on default UART HOT 11
- Atomic accesses documentation error HOT 2
- neorv32_fifo vivado implementation issue HOT 1
- Implementation problem in XILINX ISE HOT 2
- Illegal instruction in coremark HOT 5
- Utilizing on-board SRAM HOT 16
- [idea] Add indirect CSR accesses (Smcsrind ISA extension)? HOT 3
- Illegal compressed instruction reports 2 traps. HOT 7
- Variation in counter values HOT 16
- CSR reads fail for un-implemented features like HPM counters HOT 7
- Cannot upload neorv32_exe.bin for demo CFS on NexysA7 HOT 10
- Reserved compressed instructions do not trigger illegal instruction exception HOT 4
- FPU fflags no being asserted correctly HOT 15
- Instruction to halt TRNG operation HOT 2
- ERR_EXE when uploading neorv32_exe.bin for demo_blink_led on DE2-115 Board HOT 2
- FPU more fflags issues and a few logic bugs HOT 11
- Compressed instruction decoder edge case not handled HOT 3
- hpmevent_cfg_t fails synthesis for hpm_num=0 HOT 5
- c.srli HINT flagged as illegal HOT 5
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