common/common.mk : 144 main.elf Error 1

[stnolting]

common/common.mk : 144 main.elf Error 1

[kendallgreen]

I corrected a typo in --with-abi=ilp32 and recompiled the toolchain. Now make check, make info and make exe compile without error. thank you.
I have tried to map in Vivado 2020.2 the Basys3 pins to the expected signals from ProcessorTest_top.vhd and use the Basys-3-Master.xdc as the constraint file. I will keep trying
Again thanks.

[stnolting]

I have gotten as far as checking the Toolchain and Info by make check and make info in /sw/example/blink_led. But all other examples end up with the error message above.

Could you share a screenshot of your console output? If make check works as expected, then make clean_all all should also work (and generate all executable types). 🤔

I have tried the General Hardware Setup using neorv32_ProcessorTop_Test.vhd as well as neorv32_top.vhd files. In each case I can't figure out how to setup the ports for clk_i, rstn_i, gpio_0, uart0_txd0 and uart0_rxd0 for the Basys3. I think the ports are W5, W8, U16, B18 and A18 respective. I need some help.

So you are using this board: https://reference.digilentinc.com/programmable-logic/basys-3/start
Right? This page provides the schematic and also a link to the XDC file, which represents the pin mappings.

I just had a quick look at the master xdc file. You could connect neorv32_ProcessorTop_Test.vhd in the following way:

• clk_i pin W5 (100 Mhz)
• rstn_i pin U18 (button "center", low-active)
• gpio(0) pin U16 (LED0)
• gpio(1) ...
• uart0_txd_o pin B18; uart0_rxd_i pin A18 (maybe these need to be switched)

Please double check these mapping - maybe I looked too fast 😉

[kendallgreen]

make check output is exactly as in the User guide. here is the output from make info in sw/example/blink_led.
---------------- Info: Project ----------------
Project folder: blink_led
Source files: ./main.c ./blink_led_in_asm.S
Include folder(s): -I .
ASM include folder(s): -I .
---------------- Info: NEORV32 ----------------
NEORV32 home folder (NEORV32_HOME): ../../..
IMAGE_GEN: ../../../sw/image_gen/image_gen
Core source files:
../../../sw/lib/source/neorv32_wdt.c ../../../sw/lib/source/neorv32_rte.c ../../../sw/lib/source/neorv32_neoled.c ../../../sw/lib/source/neorv32_xirq.c ../../../sw/lib/source/neorv32_slink.c ../../../sw/lib/source/neorv32_twi.c ../../../sw/lib/source/neorv32_uart.c ../../../sw/lib/source/neorv32_spi.c ../../../sw/lib/source/neorv32_cfs.c ../../../sw/lib/source/neorv32_pwm.c ../../../sw/lib/source/neorv32_cpu.c ../../../sw/lib/source/neorv32_mtime.c ../../../sw/lib/source/neorv32_trng.c ../../../sw/lib/source/neorv32_gpio.c ../../../sw/common/crt0.S
Core include folder:
../../../sw/lib/include
---------------- Info: Objects ----------------
Project object files:
./main.c.o ./blink_led_in_asm.S.o ../../../sw/lib/source/neorv32_wdt.c.o ../../../sw/lib/source/neorv32_rte.c.o ../../../sw/lib/source/neorv32_neoled.c.o ../../../sw/lib/source/neorv32_xirq.c.o ../../../sw/lib/source/neorv32_slink.c.o ../../../sw/lib/source/neorv32_twi.c.o ../../../sw/lib/source/neorv32_uart.c.o ../../../sw/lib/source/neorv32_spi.c.o ../../../sw/lib/source/neorv32_cfs.c.o ../../../sw/lib/source/neorv32_pwm.c.o ../../../sw/lib/source/neorv32_cpu.c.o ../../../sw/lib/source/neorv32_mtime.c.o ../../../sw/lib/source/neorv32_trng.c.o ../../../sw/lib/source/neorv32_gpio.c.o ../../../sw/common/crt0.S.o
---------------- Info: RISC-V CPU ----------------
MARCH: -march=rv32i
MABI: -mabi=ilp32
---------------- Info: Toolchain ----------------
Toolchain:
CC: riscv32-unknown-elf-gcc
OBJDUMP: riscv32-unknown-elf-objdump
OBJCOPY: riscv32-unknown-elf-objcopy
SIZE: riscv32-unknown-elf-size
---------------- Info: Compiler Libraries ----------------
LIBGCC:
/opt/riscv/lib/gcc/riscv32-unknown-elf/11.1.0/libgcc.a
SEARCH-DIRS:
install: /opt/riscv/lib/gcc/riscv32-unknown-elf/11.1.0/
programs: =/opt/riscv/libexec/gcc/riscv32-unknown-elf/11.1.0/:/opt/riscv/libexec/gcc/riscv32-unknown-elf/11.1.0/:/opt/riscv/libexec/gcc/riscv32-unknown-elf/:/opt/riscv/lib/gcc/riscv32-unknown-elf/11.1.0/:/opt/riscv/lib/gcc/riscv32-unknown-elf/:/opt/riscv/lib/gcc/riscv32-unknown-elf/11.1.0/../../../../riscv32-unknown-elf/bin/riscv32-unknown-elf/11.1.0/:/opt/riscv/lib/gcc/riscv32-unknown-elf/11.1.0/../../../../riscv32-unknown-elf/bin/
libraries: =/opt/riscv/lib/gcc/riscv32-unknown-elf/11.1.0/:/opt/riscv/lib/gcc/riscv32-unknown-elf/11.1.0/../../../../riscv32-unknown-elf/lib/riscv32-unknown-elf/11.1.0/:/opt/riscv/lib/gcc/riscv32-unknown-elf/11.1.0/../../../../riscv32-unknown-elf/lib/:/opt/riscv/riscv32-unknown-elf/lib/riscv32-unknown-elf/11.1.0/:/opt/riscv/riscv32-unknown-elf/lib/:/opt/riscv/riscv32-unknown-elf/usr/lib/riscv32-unknown-elf/11.1.0/:/opt/riscv/riscv32-unknown-elf/usr/lib/
---------------- Info: Flags ----------------
USER_FLAGS:
CC_OPTS: -march=rv32i -mabi=ilp32 -Os -Wall -ffunction-sections -fdata-sections -nostartfiles -mno-fdiv -Wl,--gc-sections -lm -lc -lgcc -lc -falign-functions=4 -falign-labels=4 -falign-loops=4 -falign-jumps=4
---------------- Info: Host Native GCC Flags ----------------
CC_X86: g++ -Wall -O -g

make clean_all all gives the following:
make clean_all all
/opt/riscv/lib/gcc/riscv32-unknown-elf/11.1.0/../../../../riscv32-unknown-elf/bin/ld: /opt/riscv/lib/gcc/riscv32-unknown-elf/11.1.0/libgcc.a(muldi3.o): can't link double-float modules with soft-float modules
/opt/riscv/lib/gcc/riscv32-unknown-elf/11.1.0/../../../../riscv32-unknown-elf/bin/ld: failed to merge target specific data of file /opt/riscv/lib/gcc/riscv32-unknown-elf/11.1.0/libgcc.a(muldi3.o)
/opt/riscv/lib/gcc/riscv32-unknown-elf/11.1.0/../../../../riscv32-unknown-elf/bin/ld: /opt/riscv/lib/gcc/riscv32-unknown-elf/11.1.0/libgcc.a(multi3.o): can't link double-float modules with soft-float modules
/opt/riscv/lib/gcc/riscv32-unknown-elf/11.1.0/../../../../riscv32-unknown-elf/bin/ld: failed to merge target specific data of file /opt/riscv/lib/gcc/riscv32-unknown-elf/11.1.0/libgcc.a(multi3.o)
/opt/riscv/lib/gcc/riscv32-unknown-elf/11.1.0/../../../../riscv32-unknown-elf/bin/ld: /opt/riscv/lib/gcc/riscv32-unknown-elf/11.1.0/libgcc.a(div.o): can't link double-float modules with soft-float modules
/opt/riscv/lib/gcc/riscv32-unknown-elf/11.1.0/../../../../riscv32-unknown-elf/bin/ld: failed to merge target specific data of file /opt/riscv/lib/gcc/riscv32-unknown-elf/11.1.0/libgcc.a(div.o)
/opt/riscv/lib/gcc/riscv32-unknown-elf/11.1.0/../../../../riscv32-unknown-elf/bin/ld: /opt/riscv/lib/gcc/riscv32-unknown-elf/11.1.0/../../../../riscv32-unknown-elf/lib/libc.a(lib_a-memcpy.o): can't link double-float modules with soft-float modules
/opt/riscv/lib/gcc/riscv32-unknown-elf/11.1.0/../../../../riscv32-unknown-elf/bin/ld: failed to merge target specific data of file /opt/riscv/lib/gcc/riscv32-unknown-elf/11.1.0/../../../../riscv32-unknown-elf/lib/libc.a(lib_a-memcpy.o)
collect2: error: ld returned 1 exit status
make: *** [../../common/common.mk:144: main.elf] Error 1

Yes I am using the Basys3 from Digilent. I set up the neorv32_ProcessorTop_Test.vhd as you described, except I only set gpio(0) to U16.

[stnolting]

can't link double-float modules with soft-float modules

This is a problem with the toolchain. Please run riscv32-unknown-elf-gcc -v and post the console output (I should add that to make info).

Did you download a pre-compiled toolchain or did you build that by yourself? Alternatively, you can use this prebuilt toolchain: https://github.com/stnolting/riscv-gcc-prebuilt

[kendallgreen]

riscv32-unknown-elf-gcc -v
Using built-in specs.
COLLECT_GCC=riscv32-unknown-elf-gcc
COLLECT_LTO_WRAPPER=/opt/riscv/libexec/gcc/riscv32-unknown-elf/11.1.0/lto-wrapper
Target: riscv32-unknown-elf
Configured with: /home/ken/riscv-gnu-toolchain/riscv-gcc/configure --target=riscv32-unknown-elf --prefix=/opt/riscv --disable-shared --disable-threads --enable-languages=c,c++ --with-system-zlib --enable-tls --with-newlib --with-sysroot=/opt/riscv/riscv32-unknown-elf --with-native-system-header-dir=/include --disable-libmudflap --disable-libssp --disable-libquadmath --disable-libgomp --disable-nls --disable-tm-clone-registry --src=.././riscv-gcc --disable-multilib --with-abi=ilp32d --with-arch=rv32gc --with-tune=rocket 'CFLAGS_FOR_TARGET=-Os -mcmodel=medlow' 'CXXFLAGS_FOR_TARGET=-Os -mcmodel=medlow'
Thread model: single
Supported LTO compression algorithms: zlib
gcc version 11.1.0 (GCC)

I built the toolchain as you described in the User guide.

[kendallgreen]

Here is the entity portion of the neorv32_ProcesssorTop_test.vhd
entity neorv32_ProcessorTop_Test is
port (
-- Global control --
clk_i : in std_ulogic := 'W5'; -- global clock, rising edge
rstn_i : in std_ulogic := 'W8'; -- global reset, low-active, async
-- GPIO --
gpio_o : out std_ulogic_vector(7 downto 0) := 'U16'; -- parallel output
-- UART0 --
uart0_txd_o : out std_ulogic :='B18'; -- UART0 send data
uart0_rxd_i : in std_ulogic := 'A18'; -- UART0 receive data
);
end entity;

[stnolting]

This is the problem:
--with-abi=ilp32d --with-arch=rv32gc

The toolchain was build only for a rv32gc machine and only for the ilp32d ABI.

• rv32gc: the g extension requires extensions like f, which is not supported by the NEORV32
• ilp32d is a hardware floating-point ABI that is not compatible to machines without the f extensions (like the NEORV32)

You need to compile the toolchain with rv32i (base architecture only) and ilp32 (32-bit soft-float ABI):
📚 UG: Building the toolchain from scratch

riscv-gnu-toolchain$ ./configure --prefix=/opt/riscv --with-arch=rv32i –-with-abi=ilp32
riscv-gnu-toolchain$ make

You do not have to build the toolchain by yourself. You can use the one I have build: https://github.com/stnolting/riscv-gcc-prebuilt But note that this prebuilt toolchain does not use the latest GCC and binutils.

---

Here is the entity portion of the neorv32_ProcesssorTop_test.vhd

You need to do the signal -> pin mapping in Vivado and not in the actual VHDL file. Maybe this can help: https://forums.xilinx.com/t5/Implementation/Pin-assignment/td-p/735164

Put simple: Use the Basys-3-Master.xdc file, remove all pins that are not used, replace the default net names by the NEORV32 top signal names (for example for the clock signal: replace clk by clk_i) and add this file to your Vivado project.

[stnolting]

Great to hear! 👍

Let's keep this open for a while in case you have any further questions.

[kendallgreen]

Thanks. I need help matching the basys3 ports with the neorv32 signals.

…

On Tue, Aug 10, 2021, 12:51 PM stnolting ***@***.***> wrote: Great to hear! 👍 Let's keep this open for a while in case you have any further questions. — You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub <#138 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AAEE7TMY37ZS3KAOUIXMGI3T4FKKBANCNFSM5B2FJYPA> . Triage notifications on the go with GitHub Mobile for iOS <https://apps.apple.com/app/apple-store/id1477376905?ct=notification-email&mt=8&pt=524675> or Android <https://play.google.com/store/apps/details?id=com.github.android&utm_campaign=notification-email> .

[kendallgreen]

OK. Starting from scratch, I followed the General Hardware Setup including step 5 neorv32_ProcessorTop_Test.vhd. I followed listing 2, not changing the Memory configurations. I couldn't find neorv32_test_setup.vhd file (Page not found Error 404). Could you point me to the file?

[stnolting]

Sorry for the late answer...

OK. Starting from scratch, I followed the General Hardware Setup including step 5 neorv32_ProcessorTop_Test.vhd. I followed listing 2, not changing the Memory configurations. I couldn't find neorv32_test_setup.vhd file (Page not found Error 404). Could you point me to the file?

Seems like the is a dead link... :( We are currently reworking the test setups (see #136). You can use the neorv32_test_setup_bootloader.vhd file from that PR if you like. I think #136 will (should) be merged this weekend. The PR adds more details to the user guide to simplify an initial setup (from scratch) and also adds two new test setups that are illustrated in the user guide.

Anyway, the "current" / "classic" test setup is here: rtl/templates/processor/neorv32_ProcessorTop_Test.vhd.

[stnolting]

The new test setups have been merged into the master branch.

Here are the new setups: rtl/test_setups
Please have a look at the reworked User Guide section: https://stnolting.github.io/neorv32/ug/#_general_hardware_setup

[kendallgreen]

Thanks. I am taking a break from fpga development

…

On Sat, Aug 14, 2021, 1:43 PM stnolting ***@***.***> wrote: The new test setups have been merged into the master branch. Here are the new setups: rtl/test_setups <https://github.com/stnolting/neorv32/tree/master/rtl/test_setups> Please have a look at the reworked User Guide section: https://stnolting.github.io/neorv32/ug/#_general_hardware_setup — You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub <#138 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AAEE7TNXF3MWMQFKXCFOOA3T42TLBANCNFSM5B2FJYPA> . Triage notifications on the go with GitHub Mobile for iOS <https://apps.apple.com/app/apple-store/id1477376905?ct=notification-email&mt=8&pt=524675> or Android <https://play.google.com/store/apps/details?id=com.github.android&utm_campaign=notification-email> .

[stnolting]

I am closing this. Do not hesitate to open a new issue or discussion in case you come back to this project. 😉