neorv32_wdt component not VHDL-08 compliant

[stnolting]

neorv32_wdt component not VHDL-08 compliant

[tmeissner]

I have a IceZero board with a Lattice ICE40HX on it which is supported by the open source flow. I will try to implement neorv32 on it and make a contribution to the boards/ folder.

The ICE40HX device is pretty limited regarding embedded RAM. Maybe I simply try to port the existing UPduino v3 project to the open source implementation flow.

[umarcor]

I have an icestick (maybe too small), a FOMU (UP5K) and an EOS S3 (maybe too small). I have the icestick and FOMU toolchains ready. Either on Windows (https://hdl.github.io/MINGW-packages/) or through containers (https://hdl.github.io/containers). I helped setup CI in antonblanchard/microwatt. I'd be happy to jump in and help enhance the CI plumbing in this regard, after Torsten is done with his contributions (so that we don't overlap).

Moreover, in the mid term, I would be interested in testing neorv32 on PYNQ-Z1, microzed and KC705.

@stnolting I pinged you in gitter.im/vhdl/General. Would be nice to have a chat!

[stnolting]

@tmeissner

I have a IceZero board with a Lattice ICE40HX on it which is supported by the open source flow. I will try to implement neorv32 on it and make a contribution to the boards/ folder.
The ICE40HX device is pretty limited regarding embedded RAM. Maybe I simply try to port the existing UPduino v3 project to the open source implementation flow.

I'm very excited to hear that and I am curious what you will come up with! 👍

@umarcor

I have an icestick (maybe too small), a FOMU (UP5K) and an EOS S3 (maybe too small). I have the icestick and FOMU toolchains ready. Either on Windows (https://hdl.github.io/MINGW-packages/) or through containers (https://hdl.github.io/containers). I helped setup CI in antonblanchard/microwatt.

Now that's a great collection of EDA tools I was not aware of. I definitely have to check things out!

Moreover, in the mid term, I would be interested in testing neorv32 on PYNQ-Z1, microzed and KC705.

Should not be too hard to port one of the existing Xilinx setups - but feel free to start a new issue or discussion if you are encountering any problems.

I pinged you in gitter.im/vhdl/General. Would be nice to have a chat!

Cool! Thank you very much! Unfortunately, I have never used gitter before...
I'm not at home right now but as soon as I am back I will dig into it and respond 😉

[stnolting]

Thanks for the hint! I will fix that.

If you're interested I could contribute to synthesize the project with Yosys & GHDL.

That would be great! Experimenting with the GHDL Yosys plugin is already on my to-do list, but I haven't really looked at it yet...

Nice project by the way 🙂

Thanks again 😉

[stnolting]

I think this can be closed?

[tmeissner]

Yes, this can be closed.