Comments (4)
A stack overflow error in GHDL can occur if you are running out of memory due to too many simulated signals. GHDL uses several bytes for each signal and you might get problems when simulating large memories. There are simulation-optimized versions of the IMEM and DMEM components, that use constants/variables instead of the 'signals' for the memory array: sim/rtl_modules
The default testbench features a simulated UART receiver. Eachprintable char that is received from the processor's UART will be printed to the console and also written to neorv32.testbench_uart.out
.
If the UART is in simulation mode (setting bit 12 in the UART control register), the actual UART transmitter logic will be disabled. All data written to the UART's TX data register will be "printed" using VHDL text.io (which is way faster than using the testbench simulated UART receiver):
- The printable ASCII char will be printed to the console and also to
neorv32.testbench_uart.out
. - The full 32-bit word written to the UART'S TX data register will be printed as hex word to
neorv32.uart.sim_mode.data.out
.
You can automatically activate the simulation mode by using USER_FLAGS+=-DUART_SIM_MODE
when compiling your applications.
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Is your simulation now working as expected? 🤔
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I'm also working with Arty and E0-nano. So if you need any help, feel free to get in contact again. 😉
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Related Issues (20)
- Illegal compressed instruction reports 2 traps. HOT 7
- Variation in counter values HOT 16
- CSR reads fail for un-implemented features like HPM counters HOT 7
- Cannot upload neorv32_exe.bin for demo CFS on NexysA7 HOT 10
- Reserved compressed instructions do not trigger illegal instruction exception HOT 4
- FPU fflags no being asserted correctly HOT 15
- Instruction to halt TRNG operation HOT 2
- ERR_EXE when uploading neorv32_exe.bin for demo_blink_led on DE2-115 Board HOT 2
- FPU more fflags issues and a few logic bugs HOT 11
- Compressed instruction decoder edge case not handled HOT 3
- hpmevent_cfg_t fails synthesis for hpm_num=0 HOT 5
- c.srli HINT flagged as illegal HOT 5
- Simulation hangs HOT 16
- Possible issue with FIRQ pending interrupt clearing HOT 14
- Duplicate driver for s1_axis_tvalid_int in neorv32_SystemTop_axi4lite.vhd HOT 2
- Vivado warnings/errors for SLINK AXI stream interface clocks HOT 5
- Possible SLINK RX FIFO overflow HOT 3
- [feature request] add *.f file to track all HDL files + compile order HOT 10
- [VHDL] more than one module per file - a bad idea? HOT 5
- [feature request] add Rust support HOT 4
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