strath-sdr/rfsoc_radio

PYNQ example of using the RFSoC as a QPSK/BPSK radio transceiver.

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RFSoC Radio Transceiver

This repository is compatible with PYNQ images v2.7 and higher for the following RFSoC development boards:

• ZCU208,
• ZCU216,
• ZCU111,
• RFSoC4x2.
• RFSoC2x2,

Introduction

This repository contains a BPSK & QPSK transceiver radio design for RFSoC platforms. The radio is capable of transmitting and receiving BPSK & QPSK modulated waveforms in loopback, or between RFSoC development boards running the same design. A simple "hello world" example is presented demonstrating that transmitted waveforms can be received, synchronised, and the payload extracted for analysis. Check out the demonstration below and the quick start guide to install the project on your RFSoC platform.

Quick Start

Follow the instructions below to install the radio demonstrator on your development board. You will need to give your board access to the internet.

• Power on your RFSoC development board with an SD Card containing a fresh PYNQ v2.7 image or higher.
• Navigate to Jupyter Labs by opening a browser (preferably Chrome) and connecting to http://<board_ip_address>:9090/lab.
• We need to open a terminal in Jupyter Lab. Firstly, open a launcher window as shown in the figure below:

• Now open a terminal in Jupyter as illustrated below:

• Now simply install the radio demonstrator through PIP by executing the following command in the terminal:

pip3 install https://github.com/strath-sdr/rfsoc_radio/releases/download/v0.3.4/rfsoc_radio.tar.gz
python -m rfsoc_radio install

Once installation has complete, you will find the radio demonstrator notebooks located in the jupyter home workspace in the rfsoc_radio folder.

Using the Project Files

The following software is required to use the project files in this repository.

• Vivado Design Suite 2020.2
• System Generator for DSP
• MATLAB R2020a

System Generator

The Tx and Rx IPs are in separate directories in rfsoc_radio/boards/ip/sysgen/ that can be opened using the appropriate System Generator dialogue. Due to the large amount of decimation and interpolation in both IPs, simulating the output can take an extraordinarily long time. A less extreme multirate system would simulate much faster!

Vivado

This project can be built with Vivado from the command line. Open Vivado 2020.2 and execute the following into the tcl console:

cd /<repository-location>/boards/<board-name>/rfsoc_radio/

Now that we have moved into the correct directory, make the Vivado project by running the make commands below sequentially.

make block_design
make bitstream

Alternatively, you can run the entire project build by executing the following into the tcl console:

make all

License

BSD 3-Clause

rfsoc_radio's Issues

Add the ZCU670 Development Board

With or without the CLK104 board.

Regarding the configuration for external PLL clock

Hi! Thank you for providing such an informative example for researchers working in the field of SDR. I noticed that the register files for configuring the external PLL clock are located at rfsoc_radio/xrfclk/lmk04828. I wondered how do you generate those files? and how to change the configuration so that a higher sampling frequency can be achieved?

open the project with vivado 2020.2

Try the following procedure "make block_design" with no sucsess
mybe you have the XPR file?

cd /Users/erez/rfsoc_sam-master/boards/RFSoC4x2/rfsoc_sam/
make all

WARNING: [Common 17-259] Unknown Tcl command 'make all' sending command to the OS shell for execution. It is recommended to use 'exec' to send the command to the OS shell.
vivado -mode batch -source make_block_design.tcl -notrace

****** Vivado v2020.2 (64-bit)
**** SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
**** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source make_block_design.tcl -notrace
INFO: [Common 17-206] Exiting Vivado at Sun Sep 25 13:37:07 2022...
ERROR: [Board 49-71] The board_part definition was not found for xilinx.com:rfsoc4x2:part0:1.0. The project's board_part property was not set, but the project's part property was set to xczu48dr-ffvg1517-2-e. Valid board_part values can be retrieved with the 'get_board_parts' Tcl command. Check if board.repoPaths parameter is set and the board_part is installed from the tcl app store.
make.EXE: *** [makefile:4: block_design] Error 1
ambiguous command name "make": make_diff_pair_ports make_wrapper