systemviewinc/visual-system-integrator

Visual System Integrator - Accelerate your embedded development

Visual System Integrator - Accelerate your embedded development

Visual System Integrator is the one-of-a-kind tool for embedded development which, for the first time, makes it possible to develop a full functioning system. Visual System Integrator enables you to define the full system using GUI or through a C++ file. The defined system can span across multiple CPUs, FPGAs and DSPs from different vendors.

Visual System Integrator provides system level instrumentation and trace capabilities throughout the system and across vendor specific tools to reduce time-to-market.

Visual System Integrator provides code import support for popular languages such as C++. python and java. By using Visual System Integrator, moving data between these programming languages and even across software/hardware is as simple as drawing a line. The end result is reduced time in repetitive tasks and more time developing features and making your product robust.

Where is the source code?

Visual System Integrator is a set of components that make it easier and faster to compose Embedded Systems visually. We've already open sourced several components that could be found at our public repositories at [https://github.com/systemviewinc].

This repository is mainly used to report issue and provide feedback.

Status

Build

Job	Status
Driver Rpmsg
Driver Vsi
Linux-Xlnx
Vsi

Integration

Job	Status
R5
Sobel Algorithm
Blocking Read
Cxx Api
Cxx Api Device Automatic Passthrough
Cxx Api Device Hw
Cxx Api Device Passthrough
Cxx Api Multi Sw
Cxx Api Passthrough
Data Transfer
Java Api Device Passthrough
Java Arm
Python Api Device Passthrough
Python Device
Python Regression
Simulation
Sort
Sort Arm
Univariate Linear Regression

visual-system-integrator's Issues

Verify working back pressure

https://trello.com/c/MTyKt9Hn/111-verify-working-back-pressure

Add more DMAs to common_interface (use hierarchy)

https://trello.com/c/uYGRnpoG/151-add-more-dmas-to-common-interface-use-hierarchy

file parameter for vsi_gen_ip

https://trello.com/c/OK1wNSRI/116-file-parameter-for-vsi-gen-ip

hardcoded control address

https://trello.com/c/CmErBnZR/104-hardcoded-control-address

mmap for rpmsg driver

https://trello.com/c/Y8jg1h2U/117-mmap-for-rpmsg-driver

Create a kconfig gile

https://trello.com/c/PTQEEYFt/143-create-a-kconfig-gile

Add last signal in axi-stream

https://trello.com/c/rXACVMan/108-add-last-signal-in-axi-stream

Create IP for multiple buffer depth in random access type (block ram)

https://trello.com/c/Z4KL5QCf/112-create-ip-for-multiple-buffer-depth-in-random-access-type-block-ram

Timesync for trace

https://trello.com/c/dp5tDZdO/115-timesync-for-trace

Remove project device from project settings

Fix seek / pci_read modifying offset (when should and shouldn't it)

https://trello.com/c/2eONtNRf/122-fix-seek-pci-read-modifying-offset-when-should-and-shouldn-t-it

Infobar API (yellow bar with an action item)

BRAM ping pong buffers

https://trello.com/c/GJGXaeKA/70-bram-ping-pong-buffers

partial reconfig support in runtime

https://trello.com/c/34HVHyfX/118-partial-reconfig-support-in-runtime

Optimize PCIe Platform

https://trello.com/c/iSYYB3ux/87-optimize-pcie-platform

VSI License should have a grace period and a method to track machine IDs

https://trello.com/c/jq5tyKy6/155-vsi-license-should-have-a-grace-period-and-a-method-to-track-machine-ids

fix kmallocs in driver

https://trello.com/c/XdrSjqjy/79-fix-kmallocs-in-driver

1GE Design

https://trello.com/c/BxGu4Qbg/71-1ge-design

livsigsegv integration

https://trello.com/c/PKR5YznU/37-livsigsegv-integration

cleanup unused data structures in driver

https://trello.com/c/gKTWfZcP/80-cleanup-unused-data-structures-in-driver

Only initialize DMA buffers when needed, not all interfaces will need both a read and write buffer

https://trello.com/c/f6FjNcjq/123-only-initialize-dma-buffers-when-needed-not-all-interfaces-will-need-both-a-read-and-write-buffer

Help->About needs to display Visual System Integrator's about and licenses

Make Trace Application a static webapp

https://trello.com/c/Rdq9vv9B/154-make-trace-application-a-static-webapp

data throughput benchmarking (Zynq)

https://trello.com/c/BZ0ukw89/68-data-throughput-benchmarking

Roadmap for 2017.2

palceholder

In Software Context, make cross compile/toolchain selection a drop down menu

image processing demo

https://trello.com/c/Vio0Yzsk/66-image-processing-demo

Handle read/write error in direct read gracefully

https://trello.com/c/M2L72GXE/124-handle-read-write-error-in-direct-read-gracefully

Remove external linkage

https://trello.com/c/sgo0nwBt/144-remove-external-linkage

Javascript Support for VSI

https://trello.com/c/N1esTN8H/135-javascript-support-for-vsi

get rid of compile warnings for driver

https://trello.com/c/W61QuF2b/84-get-rid-of-compile-warnings-for-driver

AutoUpdate

https://trello.com/c/9O2J7RXB/95-autoupdate

Make the boards and part number a dropdown in Hardware Context

Clean Repo, leaving only driver files

https://trello.com/c/q17okhqL/142-clean-repo-leaving-only-driver-files

Project Summary should be VSI Specific

• Add list of platforms
  • Context lists for each platform
    • Context name and type
    • Part number for Hardware Context
    • Processor, OS, Language and Cross Compiler for Software Context

spilt trace into probe & collector

https://trello.com/c/1EXOwN2O/152-spilt-trace-into-probe-collector

Automate insertion of dts in devicetree

https://trello.com/c/j5JfTj7o/89-automate-insertion-of-dts-in-devicetree

Deal with interrupts before stream fifo init (or all inits)

https://trello.com/c/V3ma7lzK/109-deal-with-interupts-before-steam-fifo-init-or-all-inits

HW project generation based on templates

https://trello.com/c/XMkQIE8X/114-hw-project-generation-based-on-templates

Fix resource leaks (when driver exits without de-allocating)

https://trello.com/c/aQiMqEqO/145-fix-resource-leaks-when-driver-exits-without-de-allocating

On welcome screen, Selecting Example Project should be VSI Specific

• Read the list from a JSON or XML file. Ideally from a REST endpoint such as https://systemviewinc.com/blueprints (we can add more projects to it on the fly).
• When an item is selected, download the TCL file specified in the JSON/XML file and run it to create the project.

Automated license issuing and tracking dashboard

• Database backend
• Frontend

Handle scalar input for HLS blocks

https://trello.com/c/eAxWEQSa/59-handle-scalar-input-for-hls-blocks

dynamic major number for driver

https://trello.com/c/r07zcFvd/81-dynamic-major-number-for-driver

Combobox Control that can be manually typed into.

Java prerequisite on Ubuntu

https://trello.com/c/CiPFevvr/131-java-prerequisite-on-ubuntu

Switch to using VSI System.cxx for project management (open, save)

Help and Welcome screen links should be VSI Specific

• Docs -> https://systemviewinc.com/docs
• License -> https://systemviewinc.com/license
• Issues/Support -> https://systemviewinc.com/issues
• What's new -> https://systemviewinc.com/whatsnew/{version}
• Visual System Integrator web -> https://systemviewinc.com

Failed to re-import Platform into System

Problem

When the platform is re-compiled and re-imported the following error is shown:

vsi_compile_platform {/home/frma/Documents/Projekte/project01/project01.srcs/sources_1/bd/platform/platform.bd}
vsi_import_platform {/home/frma/Documents/Projekte/project01/project01.srcs/sources_1/bd/platform/platform.bd}
failed import. The design "platform" is not a valid vsi_system design

Reason:

The system is in a unsaved status (shown with the *)
-> Save the system and the re-import should work

Add SOF/USER/TDEST/TID/KEEP/other axi sideband attributes

https://trello.com/c/cHDGuIRg/110-add-sof-user-tdest-tid-keep-other-axi-sideband-attributes