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Hi,
Actually I have not explicitly implemented a interface for custom instructions. If you add a user defined instruction to the design you could firstly define it (e.g opcode) in constants.sv. Then you should decode your instruction either in decoder.sv or in compress.sv. It depends on whether your instruction has 32-bit or 16-bit format. If necessary, additional signals could be added into structures (e.g. typdef struct packed) in wires.sv. I have implemented most of my processing units in execute_stage.sv as seperated subunits (e.g. alu.sv) with appropriate inputs and outputs in wires.sv. By program output, you could send byte data to the address of uart interface. The default address of uart interface could be changed in configure.sv respectively in vendor folder. For testbench (print.sv) it's address is defined in tb/configure.sv. I hope I explained the whole thing fully. Best regards.
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