Naming convention for counter designs

[tangxifan]

Naming convention for counter designs

[tangxifan]

@anaszameer-rs Let me know what you think. See if we can apply to all the counter designs.

[anaszameer-rs]

@tangxifan Just a suggestion! Wouldn't that be great if we use resetp | resetn instead of resetb to make it more clear?
For instance,
counterdown8_async_resetp
shows a counter with the following features:
counting down
8-bit in width
Asynchronous active-high reset

[tangxifan]

@anaszameer-rs No problem for me. We should document it. Let me start documentation template this morning. Are you o.k. to write these down in the documentation?

[tangxifan]

@anaszameer-rs If we follow the naming convention of p, should we consider n for active-low signals, rather than b?

[tangxifan]

@anaszameer-rs Kindly review the documentation about the naming rules at:

https://micro-benchmark.readthedocs.io/en/latest/developer/naming_convention/#counter-design-names

If you agree, we can close this issue. The rule will be actively applied in later PRs.

[anaszameer-rs]

ous active-high reset

@tangxifan Can we add more flexibility in counter design namings considering posedge | negedge | dual edge counters?

[tangxifan]

Good catch. Please suggest and we can update naming rules.
Currently, I will not propose to add negedge and dual edge counters massively, as OpenFPGA has not been tested on these types of counters.
But sooner or later, we should have it. Therefore, naming rules can be established now.

[anaszameer-rs]

Good catch. Please suggest and we can update naming rules. Currently, I will not propose to add negedge and dual edge counters massively, as OpenFPGA has not been tested on these types of counters. But sooner or later, we should have it. Therefore, naming rules can be established now.

@tangxifan Can we add posedge | negedge | dualedge keywords for counter designs ?
for instance,
counterdown8_posedge_async_resetn

counting down
8-bit in width
counting on posedge of clock
Asynchronous active-low reset

[anaszameer-rs]

Good catch. Please suggest and we can update naming rules. Currently, I will not propose to add negedge and dual edge counters massively, as OpenFPGA has not been tested on these types of counters. But sooner or later, we should have it. Therefore, naming rules can be established now.

@tangxifan Can we add posedge | negedge | dualedge keywords for counter designs ? for instance, counterdown8_posedge_async_resetn

counting down 8-bit in width counting on posedge of clock Asynchronous active-low reset

@tangxifan Can you please confirm which naming convention should i follow for my upcoming PR for Counter designs ?

[tangxifan]

@anaszameer-rs Let's follow the naming convention you have proposed.