tangxifan/micro_benchmark

Micro Benchmarks for FPGA design verification

micro_benchmark's Issues

Naming convention for counter designs

Is your feature request related to a problem? Please describe.
As we are enriching the counter RTL designs in https://github.com/tangxifan/micro_benchmark/tree/main/simple_registers/counters ,
it is time to establish naming convention for counters.
As such, developers can identify critical technical features from the name of a counter design.

Describe the solution you'd like
A naming convention could be

   counter[down]<size>_[async|sync]_[set|reset|setb|resetb]

• keyword down represent a counting down counter
• size is an integer, indicating the number of bits for a counter
• async and sync represent the feature of reset and set signal
• set, reset, setb and resetb indicates the existence of reset/set signal as well as polarity.

For instance,

counterdown8_async_resetb

shows a counter with the following features:

• counting down
• 8-bit in width
• Asynchronous active-low reset

Redundant counter designs

Describe the bug
A clear and concise description of what the bug is.

Which part of the project is buggy

• RTL

After merging #11 , there are some redundant counter designs which can be removed at simple_registers/counters/

To Reproduce
Steps to reproduce the behavior:

1. Clone repository and checkout commit id: aa7374d

Screenshots

dut reference argument in subroutines(async functions other than @cocotb.test)

Describe the bug
A clear and concise description of what the bug is.

To Reproduce
Steps to reproduce the behavior:

1. Deploy any microbenchmark's benchmark into dv flow of alkaid_efpga
2. run the test and find the result failing
3. Cross check the converted testbench in dv/preconfig_cocotb/...

Expected behavior
Bitstreams should not be forced each time we call a subroutine

Screenshots

as you can see bitstream is forced and dut is used in reference, it gives object error, since reset_dut does not have dut in its scope
Enviornment (please complete the following information):

• OS:

• Ubuntu 18.04

• Tool:

• Synopsys IC Compiler

• Version:

Additional context
Add any other context about the problem here.

Python Lint for cocotb testbenches

Is your feature request related to a problem? Please describe.
We should set a code formatter for all the python-based cocotb testbenches, e.g., a python linter.

Describe the solution you'd like
An example lint script:

https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/dev/pylint_check.py

Deploy the python linter to CI.