包括4个基础实验和5个选做实验,因为是初学,在此之前几乎没有太多Verilog基础,所以写法奇葩,思路清奇,实验报告也有很多错误之处,主要参考了《计算机组成与设计:硬件/软件接口》,建议后来的同学如果感到困难也可以读读这本书寻求帮助,请勿抄袭。
最后一个full全系统集成实验因为调试环境欠缺外加对实验环境的不熟悉没有全部完成。
国科大计组研讨课
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