Error facing while compiling the Tiny Rocket Core

[ashutgupta28]

Error facing while compiling the Tiny Rocket Core

[jerryz123]

This is a very old Chipyard (1.5.0), and our ability to support it is limited. Can you try again with the most recent version?

[ashutgupta28]

@jerryz123
I am using chipard version 1.9.1

[jerryz123]

Did you add ZCU102 support to your own branch? I don't believe the upstream has that board supported.

[ashutgupta28]

@jerryz123
Yes. I have add ZCU102 supported files. I have also tested Rocket Core in FPGA and it is working also .
The command I am using to rocket core on FPGA is make SUB_PROEJECT=zcu102 verilog and it is working.
Similarly I have tested different configuration.

But in Tiny core even the default configuration is not working . Here I am giving make SUB_PROEJECT=zcu102 CONFIG=TInyRocketConfig verilog but it is giving me error. I am not able to find out what is the error .

[jerryz123]

It is difficult for others to help you without being able to see what you implemented.
[error] at chipyard.fpga.zcu102.ZCU102FPGATestHarness.<init>(TestHarness.scala:84) suggests that line 84 in a TestHarness.scala you implemented is the source of the problem.

[ashutgupta28]

But if this would be the case, then my different configuration is working ? Not only this I changed configuration from big core to Medium core , thats also working.
Only it is getting problem while running in Tiny Core.

I found somewhere that Rocket TinyCore uses a default scratchpad instead of a backing memory. This scratchpad 0x80000000 to 0x80003fff is overlapping with the memport's address range and I have remove the backing memory and L2 cache as well. like

class TinyRocketConfig extends Config(
  new chipyard.config.WithTLSerialLocation(
    freechips.rocketchip.subsystem.FBUS,
    freechips.rocketchip.subsystem.PBUS) ++                          // attach TL serial adapter to f/p busses
  new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++    // use incoherent bus topology
  new freechips.rocketchip.subsystem.WithNBanks(0) ++                // remove L2$
  new freechips.rocketchip.subsystem.WithNoMemPort ++                // remove backing memory
  new freechips.rocketchip.subsystem.With1TinyCore ++                // single tiny rocket-core
  new chipyard.config.AbstractConfig)

But still not able to figure out what is the issue.
Note :
My design is compiling using verilator.

[T-K-233]

I have run into similar issue when building for Arty FPGA designs.

I think TinyCore requires a vastly different configuration for the memory system compared to other Core Configs. If the resource is limited, could you try use the SmallCore?

class XXXConfig extends Config(
  ...
  new freechips.rocketchip.subsystem.WithNSmallCores(1)
  ...
)

It's still larger than TinyCore, but it shares the same system configuration as Medium and Big.

Hope this is helpful.

[lyxxcz]

Hello，I have a Xilinx ZCU102 and want to run the Rocket Core on it ，but don't know how to support it，can you tell me how you did it? Thank you.