Comments (11)
@jerryz123 Hi Jerry, I've seen your PR #1712 that add JTAG to Arty100T.
Do you have any plan for ading JTAG to VCU118?
Or could you guide me to do it myself if possible?
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I don't have immediate plans for this, but I would be happy to review PRs on this.
Does the VCU118 expose an additional JTAG interface (not the one for programming the FPGA)?
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@jerryz123 Thanks for your response. Yes it exposes an extra jag interface for debugging and there is a code for jtag harness binder in FPGA-shell. However, that didn’t become a part of rtl code for some reason. I managed to make jtag debugging possible, do you want me to PR for it?
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Yes, a PR would be greatly appreciated.
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@michael-etzkorn Thanks for your comment. I'll keep that in mind while I make PR.
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I have a question for @jerryz123 or @michael-etzkorn. I'm consued with HarnessBinder in chipyard and Overlay in fpga-shells. What this feature (pin mapping for JTAG DEBUG) should be in between them?
If it should be an overlay, where should I put the source between fpga-shell or chipyard? This is because I've seen both HarnessBinder and some custom overlays in chipyard repo.
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Hi @michael-etzkorn. Thanks for your response. I'm getting clear about fpga-shells structure. I've updated my code based on your suggestion and I can connect GDB through jtag and openocd. I used FMC module and USB adapter to connect the FPGA bord to the host PC.
I'd like to start PR process but I'd like to know if there is a process to test such as regression test before PR.
I've checked CONTRIBUTING.md but it does not have anything about testing. Would you provide any information about it?
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@jerryz123 and @michael-etzkorn, I've made PR #1796. Would you please review it?
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Related Issues (20)
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