ucchip/wiota_ap_customer

ucchip

ucchip is a fast-growing chip design company, which provides fast customization of low-cost, low power iot SoC chips and iot solutions for all industries. We can provide variety kinds of chips such as GPRS/GPS, Wiota, LTE

About wiota_ap_customer

This project is the base station side in wiota protocol and runing in the 8088 chip.

About UC8088

Features

★ Frequency range: 65MHZ ~ 1GMHZ

★ Memory: 16MB NOR, 256KB SRAM, 128KB Data SRAM embedded in BSP

★ Common peripherals supported
 2 x 16650 compatible UART.
 2 x 32 bits timer
 SPI Master, four peripheral signal selection
 4 PWM module, independent output.
 multiple gpio interface
 I2C interface.
 Three 12 bits ADC
 10 bits Voice DAC and auxiliary DAC

★ Radio frequency features
  Sensitivity is lower than -145 dbm
  17dbm PA built in

★ RISCV 32bit CPU core with float operation unit FPU
  160Mhz Maximum operation rate(except FPU and DSP communication)
  support mono periodic multiplication and hardware integer division
  support RISCV IMFC commands set and special expanded command
  FPU/DSP@131Mhz

★ Clock
  Embedded with DCXO oscillator(required to connect external crystals)
  Embedded with 32Khz RC oscillator and 32Khz crystal oscillator(required to connect external crystals)
  Embedded with PLL to double frequency of DCXO clock
  support switch DCXO/PLL clock

★ Power/chip management
  Embedded with DCDC converter
  Embedded with LDO, IO LDO
  Embedded with lithium battery
  support in-chip or out-chip temperature detection

About WloTa Protocol

WloTa (Wide-range Intetnet Of Things communicAtion Protocol) protocol designed for the wide-area wireless loT communication is chinese independent intellectual property rights completely. The core characters include large coverage, low power consumption, a large number of connections, low cost, working at 230 MHZ to 470 MHZ in sub 1G spectrum. So it is flexible and can meet the demand of Internet communication for many industries.
WIoTa protocol design fully consider the diversified characteristics of IOT, adopting flexible architecture for adapting to various application requirements. According to the network size, multiple functional entity can be combined into a hardware entities.

Work mode

★ Synchronous mode
  AP network by star, point to multipoint. the system is high efficiency and has large capacity, can provide precise timing for IOT terminal, suitable for the special frequency band such as 230 MHZ. It support hierarchical network to enlarge the network coverage.

★ Asynchronous mode
  Point to point, point to multipoint. The implementation in this mode is simple for these is no need to plan network. but the capacity is low than synchronous mode. WloTa communication protocol has also taken measures to optimize the design of the control signal and design conflict adjustable mechanism to maximize capacity in asynchronous mode .

★ MESH mode
  This is no center mode. In asynchronous mode, the support of no center radio between IOT terminals is ebable.

Contact us

Email: [email protected]

wiota_ap_customer's Issues

driver_hw_i2c.c read and write operation not incorrect, please update.

Read and Write sequence incorrect！
(1) read and write operation for device address byte not correct. both founction handle's as write operation.
(2) the operation in write and read function note as "write higth address" and " write low address" should all been treat as user data. There should be no such sequence in driver logic.
(3) a start write is not need before stop operation.

static rt_size_t i2c_hw_write(struct rt_i2c_msg *msg)
{
    unsigned int j = 0;
    unsigned int address = msg->addr & (~0x01); //0->write

    //write
    i2c_send_data(hi2c1.base, address);
    i2c_send_command(hi2c1.base, I2C_START_WRITE);
    i2c_get_ack(hi2c1.base);

    //write higth address
    i2c_send_data(hi2c1.base, msg->buf[0]);
    i2c_send_command(hi2c1.base, I2C_WRITE);
    i2c_get_ack(hi2c1.base);

    //write low address
    i2c_send_data(hi2c1.base, msg->buf[0]);
    i2c_send_command(hi2c1.base, I2C_WRITE);
    i2c_get_ack(hi2c1.base);

    for (j = 1; j < msg->len; j++)
    {
        i2c_send_data(hi2c1.base, msg->buf[j]);
        i2c_send_command(hi2c1.base, I2C_WRITE);
        i2c_get_ack(hi2c1.base);
    }
    i2c_send_command(hi2c1.base, I2C_STOP_WRITE);

    while (i2c_busy(hi2c1.base))
        ;
    //wait write data over
    do
    {
        i2c_send_data(hi2c1.base, address);
        i2c_send_command(hi2c1.base, I2C_START_WRITE);
    } while (!i2c_get_ack(hi2c1.base));
    i2c_send_command(hi2c1.base, I2C_STOP);
    while (i2c_busy(hi2c1.base))
        ;

    return 0;
}

static rt_size_t i2c_hw_read(struct rt_i2c_msg *msg)
{
    unsigned int address = msg->addr & (~0x01); //0->write
    unsigned int j = 0;
    i2c_send_data(hi2c1.base, address);
    i2c_send_command(hi2c1.base, I2C_START_WRITE);
    i2c_get_ack(hi2c1.base);


    //write higth address
    i2c_send_data(hi2c1.base, msg->buf[0]);
    i2c_send_command(hi2c1.base, I2C_WRITE);
    i2c_get_ack(hi2c1.base);

    //write low address
    i2c_send_data(hi2c1.base, msg->buf[0]);
    i2c_send_command(hi2c1.base, I2C_WRITE);
    i2c_get_ack(hi2c1.base);

    i2c_send_command(hi2c1.base, I2C_STOP);
    while (i2c_busy(hi2c1.base))
        ;

    address = msg->addr | 0x01; //1->read
    i2c_send_data(hi2c1.base, address);
    i2c_send_command(hi2c1.base, I2C_START_WRITE);
    i2c_get_ack(hi2c1.base);

    for (j = 0; j < msg->len; j++)
    {
        i2c_send_command(hi2c1.base, I2C_READ);
        i2c_get_ack(hi2c1.base);
        msg->buf[j] = i2c_get_data(hi2c1.base);
    }

    i2c_send_command(hi2c1.base, I2C_STOP_READ);
    return 0;
}

Also, take consideration when handling other operation flag in RTT. Such as RT_I2C_NO_STOP、RT_I2C_NO_START etc.

#define RT_I2C_WR                0x0000
#define RT_I2C_RD               (1u << 0)
#define RT_I2C_ADDR_10BIT       (1u << 2)  /* this is a ten bit chip address */
#define RT_I2C_NO_START         (1u << 4)
#define RT_I2C_IGNORE_NACK      (1u << 5)
#define RT_I2C_NO_READ_ACK      (1u << 6)  /* when I2C reading, we do not ACK */
#define RT_I2C_NO_STOP          (1u << 7)