umairahmadh/rtl-bites

rtl-bites

Inspired from https://github.com/raulbehl/100DaysOfRTL/tree/main

Course Content: Apologies for the confusion. Here's the revised curriculum in a markdown table format, based on your initial list:

Day	Topic	Link
1	Introduction to RTL Design
2	Introduction to Digital Logic
3	Combinational Logic Design
4	Introduction to Verilog/VHDL
5	Combinational Circuits - Multiplexers, Decoders, and Encoders
6	Sequential Logic Design - Flip-Flops and Latches
7	Designing State Machines
8	Timing Analysis and Constraints
9	Synchronous Design - Clock Domain Crossing
10	Synchronous Design - Finite State Machines
11	Asynchronous Design - Hazards and Metastability
12	Arithmetic Circuits - Adders and Subtractors
13	Arithmetic Circuits - Multipliers and Dividers
14	Memory Elements - Registers and Memories
15	Memory Elements - RAM and ROM
16	RTL ALU (Arithmetic Logic Unit)
17	RTL Floating-Point Arithmetic
18	RTL Shifters and Rotators
19	RTL Datapath Design
20	RTL Control Unit Design
21	RTL Microarchitecture
22	RTL Pipeline Design
23	RTL Hazard Detection and Forwarding
24	RTL Cache Design
25	RTL Finite State Machine Optimization Techniques
26	RTL Testing Methodologies
27	RTL Testbench Development
28	RTL Simulation and Debugging
29	RTL Formal Verification
30	RTL Clock Domain Crossing Verification
31	RTL Low-Power Design Techniques
32	RTL Verification with Assertions
33	RTL Hardware Description Languages - SystemVerilog
34	RTL Hardware Description Languages - VHDL
35	RTL FPGA Design Techniques
36	RTL ASIC Design Flow
37	RTL Synthesis and Optimization
38	RTL Design for Testability
39	RTL Design for Manufacturability
40	RTL Design for Security
41	RTL Design for Safety-Critical Applications
42	RTL Design for High-Performance Computing
43	RTL Design for Machine Learning Accelerators
44	RTL Design for IoT Applications
45	RTL Design for Automotive Applications
46	RTL Design for Wireless Communication Systems
47	RTL Design for Video and Image Processing
48	RTL Design for Audio Processing
49	RTL Design for Cryptographic Systems
50	RTL Design for Network-on-Chip (NoC) Architectures
51	RTL Design for Custom Processors
52	RTL Design for RISC-V Processors
53	RTL Design for ARM Processors
54	RTL Design for DSP (Digital Signal Processing)
55	RTL Design for Mixed-Signal Systems
56	Introduction to UVM (Universal Verification Methodology)
57	UVM Testbench Architecture
58	UVM Components - Drivers and Monitors
59	UVM Components - Sequencers and Scoreboards
60	UVM Transactions and Configuration
61	UVM Phases and Events
62	UVM Register Abstraction and Testing
63	UVM Coverage and Analysis
64	UVM Assertions and Functional Coverage
65	UVM Virtual Sequences and Sequences Libraries
66	UVM Verification Planning and Methodologies
67	UVM Advanced Topics - Sequences and Scoreboards
68	UVM Advanced Topics - Configuration and Messaging
69	UVM Advanced Topics - Advanced Techniques and Tips
70	Introduction to Formal Verification
71	Formal Verification Methodologies
72	Formal Property Specification
73	Formal Proof Techniques
74	Formal Equivalence Checking
75	Formal Bug Hunting and Debugging
76	Formal Verification for RTL Design
77	Introduction to Advanced RTL Design Topics
78	Advanced RTL Design - High-Frequency Design Techniques
79	Advanced RTL Design - Low-Power Design Techniques
80	Advanced RTL Design - Clock Domain Crossing Techniques
81	Advanced RTL Design - Timing Closure and Optimization
82	Advanced RTL Design - Circuit Reliability and Resilience
83	Advanced RTL Design - Design for Manufacturability (DFM)
84	Advanced RTL Design - Design for Testability (DFT)
85	Advanced RTL Design - Design for Security
86	Advanced RTL Design - Design for Safety-Critical Applications
87	Advanced RTL Design - Design for Automotive Applications
88	Advanced RTL Design - Design for IoT Applications
89	Advanced RTL Design - Design for AI and Machine Learning Accel.
90	Advanced RTL Design - Design for Custom Processors
91	Advanced RTL Design - Design for RISC-V Processors
92	Advanced RTL Design - Design for ARM Processors
93	Advanced RTL Design - Design for DSP (Digital Signal Proces.)
94	Advanced RTL Design - Design for Mixed-Signal Systems
95	Advanced RTL Design - Design for Network-on-Chip (NoC) Arch.
96	Advanced RTL Design - Design for FPGA and ASIC Implementation
97	Advanced RTL Design - Design for Low-Power Applications
98	Advanced RTL Design - Design for High-Performance Computing
99	Advanced RTL Design - Design for Emerging Technologies
100	Final Project - Complex RTL Design and Verification