umd-memsys/dramsim2

DRAMSim2: A cycle accurate DRAM simulator

dramsim2's Issues

Trace based Simulation

How can I create my own traces? Is there a tool that was used to create the K6, MASE traces?

Bad Alloc

Dears,

I get the below error while creating a new rank object because of adding new bankstates (nextWrite_H & nextRead_H) in BankState.h and BankState.cpp. Do you know why?

class BankState
{
ostream &dramsim_log;
public:
//Fields
CurrentBankState currentBankState;
unsigned openRowAddress;
uint64_t nextRead;
uint64_t nextWrite;
uint64_t nextRead_H;
uint64_t nextWrite_H;
uint64_t nextActivate;
uint64_t nextPrecharge;
uint64_t nextPowerUp;

BusPacketType lastCommand;
unsigned stateChangeCountdown;

//Functions
BankState(ostream &dramsim_log_);
void print();

};
}

//All banks start precharged
BankState::BankState(ostream &dramsim_log_):
dramsim_log(dramsim_log_),
currentBankState(Idle),
openRowAddress(0),
nextRead(0),
nextRead_H(0),
nextWrite(0),
nextWrite_H(0),
nextActivate(0),
nextPrecharge(0),
nextPowerUp(0),
lastCommand(READ),
stateChangeCountdown(0)
{}

Rank *r = new Rank(dramsim_log);
terminate called after throwing an instance of 'std::bad_alloc'
what(): std::bad_alloc
Aborted (core dumped)

How to make the refresh run in ROR mode?

Please give me some hints, thank you!
:)

Cannot find library

I was trying to compile the MARSSx86 with DRAMSIM and got the following error :

/usr/bin/ld : cannot find -ldramsim -L/home/user/DRAMSim2 -Wl, -rpath=/home/user/DRAMSim2
collect2 : ld returned 1 exit status

Seems like scons cannot find libdramsim.so from given path. What should I do to make it work?

simulation performance

Problem:
running a simple profiler, I see that the program spends so much time in this function:
unsigned dramsim_log2(unsigned) in SystemConfiguration.h

dramsim_log2 is used too frequently. For example, it is invoked 7 times in function addressMapping in AddressMapping.cpp, on variables that do not change at all during one simulation.

My suggestion:

1. use __builtin_clz to calculate log2
2. use pre-calculated log2 number in the program

Thanks

Is there a mailing list to discuss DRAMSim2

Hi,
I wonder whether there is a mailing list for folks to discuss DRAMSim2 problems? I compile it with following warnings.
harry@harry-MS-7599:~/workshop1/DRAMSim2 > make
g++ -DNO_STORAGE -Wall -DDEBUG_BUILD -O3 -o AddressMapping.o -c AddressMapping.cpp
g++ -DNO_STORAGE -Wall -DDEBUG_BUILD -O3 -o Bank.o -c Bank.cpp
g++ -DNO_STORAGE -Wall -DDEBUG_BUILD -O3 -o BankState.o -c BankState.cpp
g++ -DNO_STORAGE -Wall -DDEBUG_BUILD -O3 -o BusPacket.o -c BusPacket.cpp
g++ -DNO_STORAGE -Wall -DDEBUG_BUILD -O3 -o ClockDomain.o -c ClockDomain.cpp
g++ -DNO_STORAGE -Wall -DDEBUG_BUILD -O3 -o CommandQueue.o -c CommandQueue.cpp
g++ -DNO_STORAGE -Wall -DDEBUG_BUILD -O3 -o IniReader.o -c IniReader.cpp
g++ -DNO_STORAGE -Wall -DDEBUG_BUILD -O3 -o MemoryController.o -c MemoryController.cpp
g++ -DNO_STORAGE -Wall -DDEBUG_BUILD -O3 -o MemorySystem.o -c MemorySystem.cpp
g++ -DNO_STORAGE -Wall -DDEBUG_BUILD -O3 -o MultiChannelMemorySystem.o -c MultiChannelMemorySystem.cpp
g++ -DNO_STORAGE -Wall -DDEBUG_BUILD -O3 -o Rank.o -c Rank.cpp
g++ -DNO_STORAGE -Wall -DDEBUG_BUILD -O3 -o SimulatorObject.o -c SimulatorObject.cpp
g++ -DNO_STORAGE -Wall -DDEBUG_BUILD -O3 -o TraceBasedSim.o -c TraceBasedSim.cpp
TraceBasedSim.cpp: In function ‘int main(int, char**)’:
TraceBasedSim.cpp:513:16: warning: unused variable ‘dramsim_logfile’ [-Wunused-variable]
std::ostream &dramsim_logfile = memorySystem->getLogFile();
^
g++ -DNO_STORAGE -Wall -DDEBUG_BUILD -O3 -o Transaction.o -c Transaction.cpp
g++ -DNO_STORAGE -Wall -DDEBUG_BUILD -O3 -o DRAMSim AddressMapping.o Bank.o BankState.o BusPacket.o ClockDomain.o CommandQueue.o IniReader.o MemoryController.o MemorySystem.o MultiChannelMemorySystem.o Rank.o SimulatorObject.o TraceBasedSim.o Transaction.o
Built DRAMSim successfully

Maybe, I could make a patch to fix this bug ;-)

Question about DRAM timing equations table

Hi,

In your pdf DRAMSim2 Quick Reference guide, you talk about how DRAMSim2 models command timing interactions with the protocol table (figure 2). Specifically, my question is about row 3, for a row activation following a precharge to the same rank and a different bank, which the table lists should be tRP. However, when you follow the table completely and you issue a precharge, activate and read to a bank (following the timing constraints in the table), you end up with the activation happening immediately after the precharge. Shouldn't tRP be applied when the precharge was to the same rank and the same bank, not a different one, or am I reading the table wrong?

Thanks for your help.

DRAMSim2 data_storage transaction identification

DRAMSim2 can accept several requests and call_back will report their completions. This means there should be a mechanism to identify which transaction has been completed. Address may be a candidate, but it cannot guarantee unique identification when there are more than one transaction to the same location under the condition of out-of-order completion.

I am trying to use DRAMSim2 data_storage branch and is it possible to identify which transaction has been completed?

Thanks in advance.

DRAMSim2 Trace Mode not using all transactions

I am having a small issue with DRAMSim2. It does not seem to be processing all transactions. I tried running my memory trace (converted) and the sample MASE trace as follows (I matched number of cycles to the maximum in the file):

./DRAMSim2/DRAMSim -s ./DRAMSim2/system.ini.example -d DRAMSim2/ini/DDR3_micron_64M_8B_x4_sg15.ini -t mase_art.trc -S 4096 -c 14712444 -v ./blah.out > blah

The histogram data comes out like so:

20=5187
30=43
40=20
50=18
60=8
70=15
80=12
90=14
100=14
110=10
120=12
130=10
150=1

There are 38374 lines in the original. It was worse in my trace; I had over 20,000,000 transactions but only around 35000 registered. What might be going on? There are no error messages in the output, but there are a lot of NaN values.

Regarding MARSS+DRAMSIm2 interface

Hi,

In the file memoryController.cpp, the requests to DRAMSim2 , I found the isWrite flag confusing..

bool isWrite = memRequest->get_type() == MEMORY_OP_WRITE || memRequest->get_type() == MEMORY_OP_UPDATE;
bool accepted = mem->addTransaction(isWrite,physicalAddress);
queueEntry->inUse = true;
assert(accepted);

According to the Discussion in marss http://thread.gmane.org/gmane.comp.emulators.marss86/82/focus=83
MEMORY_OP_UPDATE is the one that corresponds to writes to MainMemory isnt it ? MEMORY_OP_WRITE would be send from cache to MEMORY CONTROLLER in case of a cache miss during a write to the cache... So effectively that would work as a read from MEMORY CONTROLLER . Apologize if I am wrong, But this is how I understood the mechanism to be.

#define READ_TO_PRE_DELAY

I think the READ_TO_PRE_DELAY might be incorrect

The code shows that

define READ_TO_PRE_DELAY (AL+BL/2+max(((int)tRTP),2)-2)

However, my understanding is that
for DDR2
READ_TO_PRE_DELAY = AL+BL/2+max(((int)tRTP),2)-tCCD (tCCD=2 for DDR2)
for DDR3
READ_TO_PRE_DELAY = AL+BL/2+max(((int)tRTP),4)-tCCD (tCCD=4 for DDR3)

So, I think the correct definition should be

define READ_TO_PRE_DELAY (AL+BL/2+max(((int)tRTP),(int)tCCD)-tCCD)

MARSS unbounded Transaction Queue causing ridiculous latency numbers

Added a patch to make the transaction queue unbounded which is causing hundreds of transactions to sit in the queue and accumulate latency when running Trace Based simulation at full throttle.

Need to find a workaround either in MARSS or to have some extra conditionals to enforce the transaction queue bounds if not running with MARSS.

Memory leak in BusPacket.cpp

I may be repeating something that has already been said but in the code I pulled I am facing the following problem.

The field "data" in the class BusPacket is a pointer which gets calloc'd by Bank.cpp

void *garbage = calloc(BL * (JEDEC_DATA_BUS_BITS/8),1);
((long *)garbage)[0] = 0xdeadbeef; // tracer value
busPacket->data = garbage;

The default destructor is not de-allocating it I guess. The fix is easy though.

Build issue in Mac OS X Snow Leopard

[jwilso@s919166 DRAMSim2]$ make libdramsim.so
g++ -DNO_STORAGE -Wall -DDEBUG_BUILD -O3 -DLOG_OUTPUT -fPIC -o Bank.po -c Bank.cpp
In file included from Bank.h:37,
from Bank.cpp:34:
SystemConfiguration.h:62: error: ‘uint’ does not name a type
SystemConfiguration.h:63: error: ‘uint’ does not name a type
SystemConfiguration.h:64: error: ‘uint’ does not name a type
SystemConfiguration.h:65: error: ‘uint’ does not name a type
SystemConfiguration.h:66: error: ‘uint’ does not name a type
SystemConfiguration.h:67: error: ‘uint’ does not name a type
SystemConfiguration.h:70: error: ‘uint’ does not name a type
SystemConfiguration.h:73: error: ‘uint’ does not name a type
SystemConfiguration.h:74: error: ‘uint’ does not name a type
SystemConfiguration.h:77: error: ‘uint’ does not name a type
SystemConfiguration.h:78: error: ‘uint’ does not name a type
SystemConfiguration.h:79: error: ‘uint’ does not name a type
SystemConfiguration.h:80: error: ‘uint’ does not name a type
SystemConfiguration.h:81: error: ‘uint’ does not name a type
SystemConfiguration.h:82: error: ‘uint’ does not name a type
SystemConfiguration.h:83: error: ‘uint’ does not name a type
SystemConfiguration.h:84: error: ‘uint’ does not name a type
SystemConfiguration.h:85: error: ‘uint’ does not name a type
SystemConfiguration.h:86: error: ‘uint’ does not name a type
SystemConfiguration.h:87: error: ‘uint’ does not name a type
SystemConfiguration.h:88: error: ‘uint’ does not name a type
SystemConfiguration.h:89: error: ‘uint’ does not name a type
SystemConfiguration.h:90: error: ‘uint’ does not name a type
SystemConfiguration.h:91: error: ‘uint’ does not name a type
SystemConfiguration.h:93: error: ‘uint’ does not name a type
SystemConfiguration.h:95: error: ‘uint’ does not name a type
SystemConfiguration.h:96: error: ‘uint’ does not name a type
SystemConfiguration.h:97: error: ‘uint’ does not name a type
SystemConfiguration.h:98: error: ‘uint’ does not name a type
SystemConfiguration.h:99: error: ‘uint’ does not name a type
SystemConfiguration.h:100: error: ‘uint’ does not name a type
SystemConfiguration.h:101: error: ‘uint’ does not name a type
SystemConfiguration.h:102: error: ‘uint’ does not name a type
SystemConfiguration.h:103: error: ‘uint’ does not name a type
SystemConfiguration.h:104: error: ‘uint’ does not name a type
SystemConfiguration.h:105: error: ‘uint’ does not name a type
SystemConfiguration.h:106: error: ‘uint’ does not name a type
SystemConfiguration.h:107: error: ‘uint’ does not name a type
SystemConfiguration.h:108: error: ‘uint’ does not name a type
SystemConfiguration.h:121: error: ‘uint’ does not name a type
SystemConfiguration.h:124: error: ‘uint’ does not name a type
SystemConfiguration.h:125: error: ‘uint’ does not name a type
SystemConfiguration.h:127: error: ‘uint’ does not name a type
SystemConfiguration.h:129: error: ‘uint’ does not name a type
SystemConfiguration.h:179: error: typedef ‘DRAMSim::returnCallBack_t’ is initialized (use typeof instead)
SystemConfiguration.h:179: error: ‘uint’ was not declared in this scope
SystemConfiguration.h:179: error: expected primary-expression before ‘addr’
SystemConfiguration.h:179: error: expected primary-expression before ‘clockcycle’
SystemConfiguration.h:190: error: expected constructor, destructor, or type conversion before ‘inline’
Bank.cpp:139: error: expected `}' at end of input
make: *** [Bank.po] Error 1

int 000::ReorderBufferEntry Aborted (core dumped)

When I used kernel version 2.6.32, qemu worked well.

but I try to use kernel version 3.15, qemu is not work.

---

PTLCALL type PTLCALL_ENQUEUE
MARSSx86::Command received : -run
== Loading device model file '/home/ychoijy/DRAMSim2/ini/my_dram.ini' ==
== Loading system model file '/home/ychoijy/DRAMSim2/system.ini' ==
===== MemorySystem 0 =====
CH. 0 TOTAL_STORAGE : 4096MB | 64 Ranks | 4 Devices per rank
Completed 0 cycles, 0 commits: 0 Hz, 0 insns/sec: rip 00000000004013aewriting vis file to /home/ychoijy/DRAMSim2/results/benchmark/my_dram/4GB.1Ch.64R.scheme2.open_page.32TQ.32CQ.RtB.pRank.vis
DRAMSim2 Clock Frequency =666666666Hz, CPU Clock Frequency=2700000000Hz
Completed 42000 cycles, 4848 commits: 208144 Hz, 24025 insns/sec: rip ffffffff81099cb5

qemu-system-x86_64: ptlsim/build/core/ooo-core/ooo-pipe.cpp:2109: int ooo::ReorderBufferEntry::commit(): Assertion `physreg->data' failed. Aborted (core dumped)

I don't know why qemu is not work.

please help me. thank you.

Error in long run cycles (double free or corruption )

Dears,

I get the below error after running the DRAMSim2 on long run cycles (e.g. 140 cycle). Can ypu help me why I got this error ? I know that it is due freeing a pointer twice but how can I get this pointer ?

== Pending Transactions : 235 (140)==
//// Channel [0] ////
*** Error in `./DRAMSim': double free or corruption (fasttop): 0x00000000016e1ae0 ***
======= Backtrace: =========
/lib/x86_64-linux-gnu/libc.so.6(+0x80a46)[0x7fe1e3035a46]
/usr/lib/x86_64-linux-gnu/libstdc++.so.6(_ZNSsD1Ev+0x20)[0x7fe1e3955290]
./DRAMSim[0x41e14a]
./DRAMSim[0x41d09a]
./DRAMSim[0x41d506]
./DRAMSim[0x429a54]
./DRAMSim[0x429b58]
./DRAMSim[0x42d48b]
./DRAMSim[0x42d644]
./DRAMSim[0x4347e5]
/lib/x86_64-linux-gnu/libc.so.6(__libc_start_main+0xf5)[0x7fe1e2fd6ea5]
./DRAMSim[0x403041]
======= Memory map: ========
00400000-0044d000 r-xp 00000000 fc:00 3955968 /home/ashafik/DRAMSIM/DRAMSim2/DRAMSim
0064d000-0064e000 r--p 0004d000 fc:00 3955968 /home/ashafik/DRAMSIM/DRAMSim2/DRAMSim
0064e000-0064f000 rw-p 0004e000 fc:00 3955968 /home/ashafik/DRAMSIM/DRAMSim2/DRAMSim
0064f000-00650000 rw-p 00000000 00:00 0
016a9000-016ed000 rw-p 00000000 00:00 0 [heap]
7fe1e2fb5000-7fe1e3174000 r-xp 00000000 fc:00 6033323 /lib/x86_64-linux-gnu/libc-2.17.so
7fe1e3174000-7fe1e3373000 ---p 001bf000 fc:00 6033323 /lib/x86_64-linux-gnu/libc-2.17.so
7fe1e3373000-7fe1e3377000 r--p 001be000 fc:00 6033323 /lib/x86_64-linux-gnu/libc-2.17.so
7fe1e3377000-7fe1e3379000 rw-p 001c2000 fc:00 6033323 /lib/x86_64-linux-gnu/libc-2.17.so
7fe1e3379000-7fe1e337e000 rw-p 00000000 00:00 0
7fe1e337e000-7fe1e3392000 r-xp 00000000 fc:00 6029530 /lib/x86_64-linux-gnu/libgcc_s.so.1
7fe1e3392000-7fe1e3592000 ---p 00014000 fc:00 6029530 /lib/x86_64-linux-gnu/libgcc_s.so.1
7fe1e3592000-7fe1e3593000 r--p 00014000 fc:00 6029530 /lib/x86_64-linux-gnu/libgcc_s.so.1
7fe1e3593000-7fe1e3594000 rw-p 00015000 fc:00 6029530 /lib/x86_64-linux-gnu/libgcc_s.so.1
7fe1e3594000-7fe1e3697000 r-xp 00000000 fc:00 6033269 /lib/x86_64-linux-gnu/libm-2.17.so
7fe1e3697000-7fe1e3897000 ---p 00103000 fc:00 6033269 /lib/x86_64-linux-gnu/libm-2.17.so
7fe1e3897000-7fe1e3898000 r--p 00103000 fc:00 6033269 /lib/x86_64-linux-gnu/libm-2.17.so
7fe1e3898000-7fe1e3899000 rw-p 00104000 fc:00 6033269 /lib/x86_64-linux-gnu/libm-2.17.so
7fe1e3899000-7fe1e397e000 r-xp 00000000 fc:00 1967052 /usr/lib/x86_64-linux-gnu/libstdc++.so.6.0.17
7fe1e397e000-7fe1e3b7d000 ---p 000e5000 fc:00 1967052 /usr/lib/x86_64-linux-gnu/libstdc++.so.6.0.17
7fe1e3b7d000-7fe1e3b85000 r--p 000e4000 fc:00 1967052 /usr/lib/x86_64-linux-gnu/libstdc++.so.6.0.17
7fe1e3b85000-7fe1e3b87000 rw-p 000ec000 fc:00 1967052 /usr/lib/x86_64-linux-gnu/libstdc++.so.6.0.17
7fe1e3b87000-7fe1e3b9c000 rw-p 00000000 00:00 0
7fe1e3b9c000-7fe1e3bbf000 r-xp 00000000 fc:00 6029422 /lib/x86_64-linux-gnu/ld-2.17.so
7fe1e3d98000-7fe1e3d9d000 rw-p 00000000 00:00 0
7fe1e3dba000-7fe1e3dbe000 rw-p 00000000 00:00 0
7fe1e3dbe000-7fe1e3dbf000 r--p 00022000 fc:00 6029422 /lib/x86_64-linux-gnu/ld-2.17.so
7fe1e3dbf000-7fe1e3dc1000 rw-p 00023000 fc:00 6029422 /lib/x86_64-linux-gnu/ld-2.17.so
7fff51963000-7fff51984000 rw-p 00000000 00:00 0 [stack]
7fff519e3000-7fff519e5000 r-xp 00000000 00:00 0 [vdso]
ffffffffff600000-ffffffffff601000 r-xp 00000000 00:00 0 [vsyscall]
Aborted (core dumped)

Rank.cpp loop index bug

This may be a bug. See Rank.cpp line 176:

for (size_t i=0;i<NUM_BANKS;i++)
{
bankStates[packet->bank].nextWrite = max(bankStates[packet->bank].nextWrite, currentClockCycle + max(tCCD, BL/2));
bankStates[packet->bank].nextRead = max(bankStates[packet->bank].nextRead, currentClockCycle + WRITE_TO_READ_DELAY_B);
}

should be

for (size_t i=0;i<NUM_BANKS;i++)
{
bankStates[i].nextWrite = max(bankStates[i].nextWrite, currentClockCycle + max(tCCD, BL/2));
bankStates[i].nextRead = max(bankStates[i].nextRead, currentClockCycle + WRITE_TO_READ_DELAY_B);
}

Unable to add extra fields in any class

We are trying to include few fields to some of the classes like MemoryController, BusPacket, Transaction, etc. But we are getting a segmentation fault if we add any extra field to them. On debugging error shows up at the vector reserve or vector initialization part which baffles us why this should be the case. Is this an issue of the simulator or the STL initialization which we need to take care of? Any suggestions are welcome

TOTAL_ROW_ACCESSES causes queue blockage

When the TOTAL_ROW_ACCESSES limit is hit, the CommandQueue will precharge an open bank. If this occurs after an ACTIVATE but before the associated READ or WRITE, the READ or WRITE will never complete and gets stuck in the queue. This happens because no new ACTIVATE is scheduled to re-open the row later on, causing isIssuable to always return false. The READ or WRITE is them permanently stuck in the queue and won't issue. Solution: if you close a bank due to TOTAL_ROW_ACCESSES, schedule a new ACTIVATE if there is a READ or WRITE pending on that row.

Interleaved memory

I have a research on memory, and need a interleaved memory system that can access more than one request simultaneous if there is no bank conflict. I have noticed in DRAMsim2, it will go through the command queue to find the command which accesses the idle bank and issue it every cycle. Is this the real behavior in interleaved memory system? Thanks.

About the ECC functionality in DRAMSim2

I'm wondering if you have implemented the Error Correcting Code in DRAMSim2?
I'm still looking into the codes but it seems to be a huge work to do.
I really appreciate it if you can tell me!

Address not aligned warnings from DRAMSim2 with Marss

I've been using DRAMSim2 with the Marss simulator for a few days and am currently trying to configure the machine that I want to be simulated. I have been getting some warnings and errors from DRAMSim when I change some of the machine configurations, and I'm not sure if it's a DRAMSim or Marss issue or configuration issues on my part. I've found that I can reproduce the warnings using one of the example machine configurations provided in Marss' default.conf file. These are the steps that I'm taking to reproduce the problem from scratch (worked on 6/21/12):

> git clone git://github.com/dramninjasUMD/marss.dramsim.git
> git clone git://github.com/dramninjasUMD/DRAMSim2.git
> cd DRAMSim2
> make libdramsim.so
> cp system.ini.example system.ini
> cd ../marss.dramsim
    (At this point, I first have to edit the qemu/SConstruct file: LINKFLAGS was not being set correctly, so I replaced $LINKFLAGS in the qemu_bld_action line with "-ldramsim -L/path/to/DRAMSim2 -Wl,-rpath=/path/to/DRAMSim2")
> scons c=2 dramsim=/path/to/DRAMSim2/
> ldd qemu/qemu-system-x86_64 | grep dramsim
> edit test.cfg:
   -machine private_L2
   -corefreq 2000000000
   -bench-name test
   -stats test.stats
   -logfile test.log
   -loglevel 6
> qemu/qemu-system-x86_64 -hda /path/to/ubuntu-kvm-natty-amd64.raw -m 1024 -simconfig test.cfg

In my emulated system I now run a program that switches to simulation mode, and I see the following output:

PTLCALL type PTLCALL_ENQUEUE
MARSSx86::Command received : -run
== Loading device model file
'../DRAMSim2/ini/DDR3_micron_8M_8B_x16_sg15.ini' ==
== Loading system model file '../DRAMSim2/system.ini' ==
===== MemorySystem 0 =====
CH. 0 TOTAL_STORAGE : 1024MB | 2 Ranks | 4 Devices per rank
 Completed             0 cycles,             0 commits:         0 Hz,      0 insns/sec: rip ffffffff81037f7b 00000000004149bf
writing vis file to ../DRAMSim2/results/MARSS/DDR3_micron_8M_8B_x16_sg15/1GB.1Ch.2R.scheme2.open_page.32TQ.32CQ.RtB.pRank.vis
DRAMSim2 Clock Frequency =666666666Hz, CPU Clock Frequency=2000000000Hz
WARNING: address 0x3a4eb9bf is not aligned to the request size of 64
WARNING: address 0x3a4eb9bf is not aligned to the request size of 64
WARNING: address 0x3b0b1ff8 is not aligned to the request size of 64
WARNING: address 0x3b0b1ff8 is not aligned to the request size of 64
WARNING: address 0x3a4eb9bf is not aligned to the request size of 64
...
PTLCALL type PTLCALL_ENQUEUE
MARSSx86::Command received : -stop

My short program produces around one hundred of these warnings. In this case with the private_L2 machine (specified in marss.dramsim/config/default.conf), the simulation still runs to completion despite these warnings; however, with other machine configurations, I have received "Segmentation fault (core dumped)" or "[ERROR (MemoryController.cpp:471)]: == Error - Command Bus Collision" after the warning messages, and the emulator dies.

I tried setting either/both of "ADDRESS_MAPPING_SCHEME=scheme7" and "NUM_CHANS=2" in my DRAMSim2/system.ini file, but these did not eliminate the warnings. When I change my simconfig file (marss.dramsim/test.cfg) to specify "-machine shared_l2" instead of the private_L2 machine, the warnings do not appear. This suggests that there is maybe some misconfiguration between the caches and the memory module, but I've been unable to figure out the problem (and I was surprised that it happened with the default example private_L2 machine).

I can provide the Marss .conf files or any other information that may be needed. Thanks for sharing the DRAMSim2 tool with the community.

Question

For Rank.cpp , Line 175-180 :

bankStates[packet->bank].nextActivate = max(bankStates[packet->bank].nextActivate, currentClockCycle + WRITE_TO_PRE_DELAY);
for (size_t i=0;i<NUM_BANKS;i++)
{
bankStates[packet->bank].nextWrite = max(bankStates[packet->bank].nextWrite, currentClockCycle + max(tCCD, BL/2));
bankStates[packet->bank].nextRead = max(bankStates[packet->bank].nextRead, currentClockCycle + WRITE_TO_READ_DELAY_B);
}

Can you please review this part? I think WRITE_AUTOPRE_DELAY should be used for the first part.

Generating Trace files for DRAMSim2

I would like to use DRAMSim2 in trace mode but with traces of my own applications. What tools could I use to generate a 'k6' or 'mase' trace file?

cannot create a new Transaction object

I need to use the create and object tmp of type Transaction on the below code in Memory controller.cpp

Transaction tmp;
tmp=new Transaction (transType,1,1," ",NULL);
for (int j=1; j< Trans2d[0][i].size(); j ++)
{ if (Trans2d[0][i][j].transtp == "P_MEM_WR_H" && Trans2d[0][i][j-1].transtp == "P_MEM_WR_NH" )
{ DEBUG("== We need to swap WR H and NH == ");
tmp=Trans2d[0][i][j];
Trans2d[0][i][j]=Trans2d[0][i][j-1];
Trans2d[0][i][j-1]=tmp;
}

I changed the constructor in Transaction.cpp to be

Transaction::Transaction(TransactionType transType, uint64_t addr, uint64_t pr,string transtp, void *dat) :
transactionType(transType),
address(addr),
priority (pr),
transtp(transtp),
data(dat)
{
DEBUG("== Creating new Transaction == ");
DEBUG("== transType '"<<transtp<<"' == ");
DEBUG("== address '"<<address<<"' == ");
DEBUG("== pr '"<<pr<<"' == ");
DEBUG("== data '"<<data<<"' == ");
}

Transaction::Transaction():
transactionType(transType),
address(addr),
priority (pr),
transtp(transtp),
data(dat)
{
DEBUG("== Creating new Transaction == ");
DEBUG("== transType '"<<transtp<<"' == ");
DEBUG("== address '"<<address<<"' == ");
DEBUG("== pr '"<<pr<<"' == ");
DEBUG("== data '"<<data<<"' == ");
}

But I got the below error

In file included from MemoryController.cpp:38:0:
MemoryController.h: In constructor قDRAMSim::MemoryController::MemoryController(DRAMSim::MemorySystem_, DRAMSim::CSVWriter&, std::ostream&)ق:
MemoryController.h:80:11: warning: قDRAMSim::MemoryController::dramsim_logق will be initialized after [-Wreorder]
MemoryController.h:77:41: warning: قstd::vectorstd::vector<std::vector<DRAMSim::Transaction > > DRAMSim::MemoryController::Trans2dق [-Wreorder]
MemoryController.cpp:66:1: warning: when initialized here [-Wreorder]
MemoryController.cpp:104:21: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
MemoryController.cpp: In member function قbool DRAMSim::MemoryController::addTransaction(DRAMSim::Transaction_)ق:
MemoryController.cpp:818:41: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
MemoryController.cpp:820:48: error: no match for قoperator=ق in قtmp = (std::basic_string(((const char_)" "), ((const std::allocator)(& std::allocator()))), (operator new(56ul), (, ((DRAMSim::Transaction_)))))ق
MemoryController.cpp:820:48: note: candidate is:
In file included from MemoryController.h:41:0,
from MemoryController.cpp:38:
Transaction.h:54:7: note: DRAMSim::Transaction& DRAMSim::Transaction::operator=(const DRAMSim::Transaction&)
Transaction.h:54:7: note: no known conversion for argument 1 from قDRAMSim::Transaction_ق to قconst DRAMSim::Transaction&ق
MemoryController.cpp:821:41: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
MemoryController.cpp:849:1: warning: control reaches end of non-void function [-Wreturn-type]
make: *_* [MemoryController.o] Error 1

Partial access

addTransaction() does not have any arguments regarding size of data. How can I use DRAMsim2 as a backend simulator for system model, which requires one, two, four, and eight bytes accesses? If there are anything I did not understand yet, please let me know.

DramSim2 get parameters from MARSSx86

Hi All,
To pass parameters to DramSim2 from MARSSx86, all that should be done is to add the parameters that needed when MARSSx86 addTransaction, like this:

    #ifdef SunnyBeike
        bool accepted = mem->addTransaction(isWrite,physicalAddress, param1, param2...);
    #else
        bool accepted = mem->addTransaction(isWrite,physicalAddress);
    #endif

and modify the corresponding interface the DRAMSim2 offerd.

Is this the correct way?
Thanks for your attention.

Memory Leak in BusPacket handling

Bus packets are copied (MemoryController.cpp:238) and not destroyed properly.

Really that whole piece of code should be refactored to use only pointers to avoid a bunch of extraneous copies.

Running the trace based simulation

Dears,

After cloning your repository DRAMSim2 and running traceparse.py

cd traces/
./traceparse.py K6_aoe_short.trc.gz

then return back to DRAMSim2 directory , I dont find the ./DRAMSim command
Do you know why ?

Integrate MARSSX86 With DRAMSim2 on Cigwin

Dears,

Im trying from a while to integrate the MARSS with DRAMSIM2. It gives the below error even after installing gcc 4.5.3 (x86_64-w64-mingw32-gcc-4.5.3.exe). Is there any solution ?

scons dramsim=/cygdrive/c/users/ahmed/Downloads/DRAMSIM/DRAMSim2
scons: Reading SConscript files ...
running with -j16
Checking whether the C++ compiler worksyes
yes
ERROR: Marss does not support 32 bit x86 machine.
ERROR: Please compile/run Marss on 64 bit x86 machine.

scons: *** Return of non-existent variable ''ret_str''
File "/cygdrive/c/users/ahmed/downloads/DRAMSIM/marss.dramsim/qemu/SConfigure", line 32, in exit_with_error

Integrating Gem5 with dramsim2

Hi All,

I am first year Ph.D student . I am trying to integrate the dramsim2 patch released recently by Tao Zhang located @http://www.mail-archive.com/[email protected]/msg05088.html (also attached) with gem5 for 'fs' mode (patch is integrated and tested for 'se' mode). Has anyone else tried it, if so i need some help. Below is the description of what I am trying to do.

I made changes in FSConfig.py file to set the 'physmem' to DRAMSim2 memory. Following is the change that I had to make to integrate DRAMSim2.
-======================================================================================

  #  self.physmem = SimpleMemory(range =
   #                             AddrRange(self.realview.mem_start_addr,
    #                                    size = mdesc.mem()),
     #                           conf_table_reported = True)
    self.physmem = DRAMSim2( 
                    range = AddrRange(self.realview.mem_start_addr,size=mdesc.mem()),
                    cpu_clock="2GHz",
                    deviceConfigFile = os.path.join("/home/DREXEL/rb639/PowerAgileComputing/gem5/ext/DRAMSim2/ini/DDR3_micron_16M_8B_x8_sg15.ini"),
                    systemConfigFile=os.path.join("/home/DREXEL/rb639/PowerAgileComputing/gem5/ext/DRAMSim2/system.ini.example"),
                    ) 

-======================================================================================

Once I make this change, following is the error log:
-======================================================================================
warn: This is an integrated DRAMsim v2 module
Listening for system connection on port 5900
Listening for system connection on port 3456
0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
fatal: Expected a single ATAG memory entry but got 0
@ cycle 0
[initState:build/ARM/arch/arm/linux/system.cc, line 133]
Memory Usage: 557548 KBytes
-======================================================================================
To overcome the above error, I tried giving specific start addr in 'AddrRange', I replaced

range = AddrRange(self.realview.mem_start_addr,size=mdesc.mem()),
with the following
range = AddrRange(Addr(mdesc.mem()),size=mdesc.mem()),
or
range = AddrRange(Addr('1MB'),size=mdesc.mem()),

I end up with the below error :

warn: This is an integrated DRAMsim v2 module
Listening for system connection on port 5900
Listening for system connection on port 3456
fatal: system.membus has two ports with same range:
system.physmem.port
system.bridge.slave
@ cycle 0
[recvRangeChange:build/ARM/mem/bus.cc, line 407]

Memory Usage: 554844 KBytes

We are not sure, how to resolve the above error.

FYI, We have a working version (revision 8868) of gem5 integrated with DRAMSim2 (released by Xiangyu Dong). However, we are trying to use the latest version(revision 9197) of Gem5. The code snippet from the working code is below

self.physmem = PhysicalMemory(range = AddrRange(Addr(m5.options.memsize)),

zero = True)

    self.physmem = DRAMMemory(range = AddrRange(Addr(m5.options.memsize)),
                                  zero = True, log_file = os.path.join(m5.options.outdir, "gem5dramsim2"),
                                  memory_spec = os.path.join("/archgroup/projects/poweragile/tools/gem5/ext/dramsim2/ini/DDR3_micron_32M_8B_x8_sg15.ini"),
                                  mem_clock = m5.options.memclock)#ini/DDR2_micron_32M_8B_x4_sg25E.ini"))

Code looks much similar; however DRAMsim2 wrapper interface, and gem5 to memory interface seem to have changed.

Any guidance regarding the above will be very helpful.

Thank you

DRAMSim2 data_storage branch read mismatch

DRAMSim2 data_storage branch seems not work properly.
For two consecutive Read-After-Writes, the second read does not return what has been written.

    //----------------------------- first RAW ----
    void *write_buf = malloc(32);
    for (int x=0; x<32; x++) ((unsigned char*)write_buf)[x] = x;
    mem->addTransaction(true, 0x9000, write_buf, 32);
    for (int i=0; i<5; i++) { mem->update();   }
    mem->addTransaction(false, 0x9000, NULL, 0);
    for (int i=0; i<5; i++) { mem->update();  }
  //----------------------------- second RAW ----
    write_buf = malloc(8);
    for (int x=0; x<8; x++) ((unsigned char*)write_buf)[x] = x+16;
    mem->addTransaction(true, 0x9010, write_buf, 8);
    for (int i=0; i<5; i++) {  mem->update();  }

The above reports as follows.
dramsim_test main()
ini/DDR2_micron_16M_8b_x8_sg3E
writing vis file to ../results/resultsfilename/DDR2_micron_16M_8b_x8_sg3E/2GB.1Ch.2R.scheme2.open_page.512TQ.512CQ.RtB.pRank.6.vis
[Callback] write complete: 0 0x9000 cycle=0
[Callback] read complete: 0x9000 data='00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f '
[Callback] write complete: 0 0x9010 cycle=0
[Callback] read complete: 0x9010 data='00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f '

As it shows, values returned from address 0x9010 differ from what has written.

Request size for transaction

Hi,

Does DRAMSim2 allow specifying the request size? From the source code, I observed that for misc traces, a data field is present. Is this equivalent to request size?

Thanks

DRAMSim2 with GEM5 FS mode

I have integrated DRAMSim2 with Gem5 FS mode but the linux boot process becomes very very slow and benchmark execution is almost not possible due to slow speed. I found out that the slowness is due to the fact that 'DRAMSim2' update callback is called every clock cycles even when there is no read/write request going in to the DRAMSim2.

Please can somebody tell me how to reduce the 'update' call back frequency of DRAMsim2 so that we can use it with gem5 in FS mode. Ideally I would like the update method to be called only when read/write is sent to the DRAMsim2.

Thanks.

rowbuffer hit rate issue

Hi All,

I want to use MARSSx86+DramSim2 to count the row buffer hit ratio.

Several variables were added to class BankState as follows:

#######################################################
class BankState
{
    ostream &dramsim_log; 
public:
    //Fields
          ...
    unsigned stateChangeCountdown;
     #ifdef CONFIG_SUNNY
     unsigned lastOpenRow;
         unsigned long rowBufferAccessTimes;
         unsigned long rowBufferHitTimes;
         unsigned long rowBufferMissTimes;
     #endif

    //Functions
    BankState(ostream &dramsim_log_);
    void print();
};
#######################################################

lastOpenRow is the row accessed by the last memory request to this bank. If it equals to the
row of current request to this bank, then row-buffer of this bank hits. This judgement was carried
out in the following function:

#######################################################

void Rank::receiveFromBus(BusPacket *packet)
{
                ...

    switch (packet->busPacketType)
    {

    case READ:
            #ifdef CONFIG_SUNNY
                ++bankStates[packet->bank].rowBufferAccessTimes;

                if(packet->row == bankStates[packet->bank].lastOpenRow)
                    ++bankStates[packet->bank].rowBufferHitTimes;               
                else 
                    ++bankStates[packet->bank].rowBufferMissTimes;

                bankStates[packet->bank].lastOpenRow = packet->row;
            #endif
                    ...
          case WRITE:
            #ifdef CONFIG_SUNNY
                ++bankStates[packet->bank].rowBufferAccessTimes;

                if(packet->row == bankStates[packet->bank].lastOpenRow)
                    ++bankStates[packet->bank].rowBufferHitTimes;               
                else 
                    ++bankStates[packet->bank].rowBufferMissTimes;

                bankStates[packet->bank].lastOpenRow = packet->row;
            #endif
                    ...

             }
                ...
}
#######################################################

Is this a correct way to collect the row-buffer hit ratio information in DramSim2 ?
Thanks...

Any reply is appreciated! Thanks...

Need to remove invalid mapping schemes

Several mapping schemes that don't have the column bits at the bottom of the address are invalid in DRAMSim2 (scheme4 & scheme6 are valid, the others are not).

These need to be removed and support needs to be added for split column mappings like in DRAMSim1.

CSV output for multiple channels broken

I'm not sure how I missed this earlier, but the header output for multiple channels is really broken at the moment and has been broken pretty much since the CSVWriter code was merged.

Transaction vector error

Dears,

Iam trying to create 2D transaction vector (transactionQueue). I changed the vector in MemoryController.h to be

                                                "vector<vector<Transaction *>> transactionQueue" 

Also the MemoryController.cpp to resize it to be

                                              "transactionQueue.resize(TRANS_QUEUE_DEPTH,vector<int>( 2 )"

I got the below error. Any advice please

g++ -DNO_STORAGE -Wall -DDEBUG_BUILD -O0 -g -o MemoryController.o -c MemoryController.cpp
In file included from MemoryController.h:41:0,
from MemoryController.cpp:38:
Transaction.h: In constructor قstd::vector<_Tp, _Alloc>::vector(std::vector<_Tp, _Alloc>::size_type, const value_type&, const allocator_type&) [with _Tp = DRAMSim::Transaction; _Alloc = std::allocatorDRAMSim::Transaction; std::vector<_Tp, _Alloc>::size_type = long unsigned int; std::vector<_Tp, _Alloc>::value_type = DRAMSim::Transaction; std::vector<_Tp, Alloc>::allocator_type = std::allocatorDRAMSim::Transaction]ق:
Transaction.h:56:2: error: قDRAMSim::Transaction::Transaction()ق is private
MemoryController.cpp:91:67: error: within this context
MemoryController.cpp: In constructor قDRAMSim::MemoryController::MemoryController(DRAMSim::MemorySystem, DRAMSim::CSVWriter&, std::ostream&)ق:
MemoryController.cpp:91:68: error: no matching function for call to قstd::vector<std::vectorDRAMSim::Transaction_ >::resize(unsigned int&, std::vectorDRAMSim::Transaction)ق
MemoryController.cpp:91:68: note: candidate is:
In file included from /usr/include/c++/4.7/vector:65:0,
from SystemConfiguration.h:38,
from Transaction.h:38,
from MemoryController.h:41,
from MemoryController.cpp:38:
/usr/include/c++/4.7/bits/stl_vector.h:684:7: note: void std::vector<_Tp, _Alloc>::resize(std::vector<_Tp, _Alloc>::size_type, std::vector<_Tp, _Alloc>::value_type) [with _Tp = std::vectorDRAMSim::Transaction*; Alloc = std::allocatorstd::vector<DRAMSim::Transaction* >; std::vector<Tp, Alloc>::size_type = long unsigned int; std::vector<Tp, Alloc>::value_type = std::vectorDRAMSim::Transaction*]
/usr/include/c++/4.7/bits/stl_vector.h:684:7: note: no known conversion for argument 2 from قstd::vectorDRAMSim::Transactionق to قstd::vectorstd::vector<DRAMSim::Transaction* >::value_type {aka std::vectorDRAMSim::Transaction*}ق
MemoryController.cpp: In member function قvoid DRAMSim::MemoryController::receiveFromBus(DRAMSim::BusPacket)ق:
MemoryController.cpp:144:98: error: no matching function for call to قDRAMSim::Transaction::Transaction(DRAMSim::TransactionType, uint64_t&, void&)ق
MemoryController.cpp:144:98: note: candidates are:
In file included from MemoryController.h:41:0,
from MemoryController.cpp:38:
Transaction.h:70:2: note: DRAMSim::Transaction::Transaction(const DRAMSim::Transaction&)
Transaction.h:70:2: note: candidate expects 1 argument, 3 provided
Transaction.h:69:2: note: DRAMSim::Transaction::Transaction(DRAMSim::TransactionType, uint64_t, uint64_t, void)
Transaction.h:69:2: note: candidate expects 4 arguments, 3 provided
Transaction.h:56:2: note: DRAMSim::Transaction::Transaction()
Transaction.h:56:2: note: candidate expects 0 arguments, 3 provided
MemoryController.cpp: In member function قvirtual void DRAMSim::MemoryController::update()ق:
MemoryController.cpp:514:48: error: cannot convert قstd::vectorDRAMSim::Transaction_ق to قDRAMSim::Transaction_ق in initialization
MemoryController.cpp:732:4: error: no match for قoperator_ق in ق((DRAMSim::MemoryController)this)->DRAMSim::MemoryController::transactionQueue.std::vector<Tp, Alloc>::operator[]std::vector<DRAMSim::Transaction*, std::allocatorstd::vector<DRAMSim::Transaction* > >(i)ق
MemoryController.cpp: In member function قbool DRAMSim::MemoryController::addTransaction(DRAMSim::Transaction)ق:
MemoryController.cpp:797:35: error: no matching function for call to قstd::vector<std::vectorDRAMSim::Transaction_ >::push_back(DRAMSim::Transaction&)ق
MemoryController.cpp:797:35: note: candidate is:
In file included from /usr/include/c++/4.7/vector:65:0,
from SystemConfiguration.h:38,
from Transaction.h:38,
from MemoryController.h:41,
from MemoryController.cpp:38:
/usr/include/c++/4.7/bits/stl_vector.h:881:7: note: void std::vector<_Tp, _Alloc>::push_back(const value_type&) [with _Tp = std::vectorDRAMSim::Transaction_; _Alloc = std::allocatorstd::vector<DRAMSim::Transaction* >; std::vector<_Tp, _Alloc>::value_type = std::vectorDRAMSim::Transaction*]
/usr/include/c++/4.7/bits/stl_vector.h:881:7: note: no known conversion for argument 1 from قDRAMSim::Transaction_ق to قconst value_type& {aka const std::vectorDRAMSim::Transaction_&}ق
make: *** [MemoryController.o] Error 1

NUM_RANKS and NUM_BANKS are shared among different MemorySystems

I am using DRAMsim2 as a library, and trying to build two different memory systems, one has smaller rank size, like 1, and the other has larger rank size, like 4.

I find that NUM_RANKS and NUM_BANKS are shared by above two memory systems, so that memory access violation will happen in my first 1-rank memory system. This happens in MemoryController::resetStats(), where NUM_RANKS should be 1 when 1-rank memory system is resetting, but happened to be 4.

I think NUM_RANKS, NUM_BANKS should be a member in MemorySystem and MemoryController, such that this bug can be solved.

Thanks.

Row Buffer Miss

Hi All,
I used MARSSx86+DramSim2 to got the row buffer miss rate of test suites in PARSEC. But the result is too low to be true.
I first added my code the these following methods.
void MemoryController::update()
void Rank::receiveFromBus(BusPacket *packet)
The above two methos all update bankStates in a "switch" branch. But I think the update in Rank::receiveFromBus is not appropriate. Because in the real DRAM, it is the memory controller sends the essential commands, and only one time. So, why not do some optimization to " class Rank "? While, the bankStates updated in the MemoryController::update() method seems invalid... Finally, I collect the row buffer miss information in the Rank::receiveFromBus method like this:

####################################################################
    switch (packet->busPacketType)
    {
    case READ:
    /*
        Added by SunnyBeike
    */
            #ifdef SunnyBeike
                ++bankStates[packet->bank].READ_times[privilegeState];
                if(packet->row == bankStates[packet->bank].lastOpenRowAddress) 
                    ++bankStates[packet->bank].rowBufferHitTimes[privilegeState];
                else 
                    ++bankStates[packet->bank].rowBufferMissTimes[privilegeState];
                bankStates[packet->bank].lastOpenRowAddress = packet->row;

                    #endif
    /*
        The End
    */
        ...
      }
####################################################################

The lastOpenRowAddress is a new member I added to class BankState to record the last row that was active in the row buffer. I had also added some other members to class BankState, like rowBufferHitTimes , READ_times, WRITE_times...
The code listed above was adde to busPacketType that is READ or RED_P or WRITE or WRITE_P.

So, can I get the right rowbuffer miss rate in the above way?
Thanks for your attention!

How to integrate DRAMSim2 with Eclipse IDE

I am using Eclipse IDE. i want to integrate DRAMSim2 with it. Please can you give me build settings in Eclipes IDE:

I am getting the following error:
/home/user/DRAMSim2/example_app/dramsim_test: error while loading shared libraries: libdramsim.so: cannot open shared object file: No such file or directory

Address mapping schemes

Dears,

What is the difference between schemes in addressmapping.cpp ?
On what parameters I can use one of them ?

Thanks and BR,
Ahmed Shafik

Error in Inserting in 3d Transaction vector

I created 3D vector in MemoryController.h as shown below

            vector<vector <vector< Transaction> > > Trans3d;

In MemoryController.cpp file I used the below code to resize the vector and reserve the required entries

     Trans3d.resize(2); 
 for(int i = 0; i < 2; i++) 
     {Trans3d[i].resize(TRANS_QUEUE_DEPTH);
     for(int j = 0; j< TRANS_QUEUE_DEPTH; j++) 
  {  Trans3d[i][j].reserve(2);}}

After that, to use the push back function as below

      Trans3d[0][0].push_back(trans);

This idea worked in Visual Studio. But after trying it in the simulator I got the below error

         MemoryController.cpp: In member function قbool DRAMSim::MemoryController::addTransaction(DRAMSim::Transaction*)ق:

MemoryController.cpp:815:39: error: no matching function for call to قstd::vectorDRAMSim::Transaction::push_back(DRAMSim::Transaction_&)ق
MemoryController.cpp:815:39: note: candidate is:
In file included from /usr/include/c++/4.7/vector:65:0,
from SystemConfiguration.h:38,
from Transaction.h:38,
from MemoryController.h:41,
from MemoryController.cpp:38:
/usr/include/c++/4.7/bits/stl_vector.h:881:7: note: void std::vector<_Tp, _Alloc>::push_back(const value_type&) [with _Tp = DRAMSim::Transaction; _Alloc = std::allocatorDRAMSim::Transaction; std::vector<_Tp, _Alloc>::value_type = DRAMSim::Transaction]
/usr/include/c++/4.7/bits/stl_vector.h:881:7: note: no known conversion for argument 1 from قDRAMSim::Transaction_ق to قconst value_type& {aka const DRAMSim::Transaction&}ق
MemoryController.cpp:831:1: warning: control reaches end of non-void function [-Wreturn-type]

the latency histogram in the output file only contains read latency?

hi,
Recently, I spent some time to analysis the sourcecode. I found that the latency histogram in the output file only contains read latency. Why not take write transactions into account?
thanks ,：）

PARSEC workload

Dears,

Kindly provide me with the way to connect Parsec benchmark with DRAMSim2

DRAMSim2 data_storage addTransaction arguments

DRAMSim2 data_storage branch has 'addTransction()' API to issue memory transaction.
For write transaction, addTransaction() API takes the following arguments

• isWrite
• address
• point_to_buffer
• num_of_byte

where 'point_to_buffer' should be new point for every call, since DRAMSim2 sees free somewhere while processing the request. Is it correct?

For read transaction, addTransaction() API takes the following arguments

• isWrite
• address
• point_to_buffer
• num_of_byte

where 'point_to_buffer' should be NULL and read completion callback will provide newly allocated data buffer, which should be not freed by the user program. Is it correct?

Thanks in advance for any comment.

IniReader.cpp typo

line 411: IniReader::SetKey(key, valueString, lineNumber, isSystemFile);

should be

IniReader::SetKey(key, valueString, isSystemFile, lineNumber);

Unable to successfully run scons due to undefined reference to BIT in kvm.c

I have a problem while trying to run step 2 of the MARSSx86+DRAMSim2 configuration (Go into the marss folder and type scons dramsim=/full/path/to/DRAMSim2). I have successfully resolved all previous dependency issues by installing necessary packages.

I get an undefined reference to BIT in kvm.c

john@abcd:~/marss.dramsim$ scons dramsim=/home/john/DRAMSim2
scons: Reading SConscript files ...
running with -j5
Checking whether the C++ compiler works(cached) yes
no
yes
yes
no
Checking for C library z... (cached) yes
yes
Checking for C library X11... (cached) yes
yes
Checking for C library vdeplug... (cached) no
no
Checking for C library curses... (cached) yes
Checking for C library pthread... (cached) yes
yes
Checking for C library fdt... (cached) no
yes
yes
yes
no
yes
yes
yes
yes
yes
yes
Checking for C header file signal.h... (cached) yes
Checking for C header file time.h... (cached) yes
Checking for C library rt... (cached) yes
Checking for C function fdatasync()... (cached) yes
yes
yes
yes
yes
Checking for C library attr... (cached) no
yes
yes
yes
Checking for C library sasl... (cached) no
Checking for C header file byteswap.h... (cached) yes
Checking for C header file machine/bswap.h... (cached) no
Machine 'shared_l2' requires minimum of 2 contexts while you are compiling with 1 contexts. Skipping this machine 'shared_l2'.
Machine 'ooo_2_th' requires minimum of 2 contexts while you are compiling with 1 contexts. Skipping this machine 'ooo_2_th'.
Machine 'moesi_private_L2' requires minimum of 2 contexts while you are compiling with 1 contexts. Skipping this machine 'moesi_private_L2'.
Machine 'private_L2' requires minimum of 2 contexts while you are compiling with 1 contexts. Skipping this machine 'private_L2'.
Plugins found :
scons: done reading SConscript files.
scons: Building targets ...
Linking Program ==> qemu/qemu-system-x86_64
qemu/libqemu_common.a(misc.o): In function slirp_connection_info': misc.c:(.text+0x917): warning: memset used with constant zero length parameter; this could be due to transposed parameters qemu/target-i386/kvm.o: In functionkvm_arch_init_vcpu':
kvm.c:(.text+0x1ed6): undefined reference to BIT' kvm.c:(.text+0x1ee5): undefined reference toBIT'
kvm.c:(.text+0x1f60): undefined reference to BIT' kvm.c:(.text+0x2111): undefined reference toBIT'
kvm.c:(.text+0x2181): undefined reference to BIT' qemu/target-i386/kvm.o:kvm.c:(.text+0x21f1): more undefined references toBIT' follow
collect2: error: ld returned 1 exit status
scons: *** [qemu/qemu-system-x86_64] Error 1
scons: building terminated because of errors.

cannot view the data after adding to vector

Dears,

Kindly need your support as after creation of 3D vector and adding the Transaction object to it, I can't view the data to use although it is working fine on visual studio

Trans2d.resize(2);
for(int i = 0; i < 2; i++)
{Trans2d[i].resize(TRANS_QUEUE_DEPTH);
for(int j = 0; j< TRANS_QUEUE_DEPTH; j++)
{//Trans[j].resize(2);
Trans2d[i][j].reserve(4);}}

bool MemoryController::addTransaction(Transaction _trans)
{
if (WillAcceptTransaction(trans))
{
if ((_trans).priority == 1 )
{
DEBUG("== currentClockCycle '"<<currentClockCycle<<"' == ");
trans->timeAdded = currentClockCycle;
if ((_trans).transtp == "P_MEM_WR_H" || (_trans).transtp == "P_MEM_WR_NH")
{Trans2d[0][0].push_back(_trans);
DEBUG("== Trans2d[0][0][0].transtp '"<<Trans2d[0][0][0].transtp<<"' == ");}
else {
Trans2d[0][1].push_back(_trans);}
for ( int i = 0; i < Trans2d[0].size(); i++) {
Transaction tmp;
DEBUG("== [i] '"<<i<<"' == ");
//tmp=new Transaction (transType,1,1," ",NULL);
for (int j=1; j< Trans2d[0][i].size(); j ++)
{
DEBUG("== [j] '"<<j<<"' == ");
DEBUG("== Trans2d[0][0][0].transtp '"<<Trans2d[0][0][0].transtp<<"' == ");//the data here appears null
if (Trans2d[0][i][j].transtp == "P_MEM_WR_H" && Trans2d[0][i][j-1].transtp == "P_MEM_WR_NH" )
{ DEBUG("== We need to swap WR H and NH == ");
tmp=Trans2d[0][i][j];
Trans2d[0][i][j]=Trans2d[0][i][j-1];
Trans2d[0][i][j-1]=tmp;
}
else if (Trans2d[0][i][j].transtp == "P_MEM_RD_H" && Trans2d[0][i][j-1].transtp == "P_MEM_RD_NH" )
{ DEBUG("== We need to swap RD H and NH == ");
tmp=Trans2d[0][i][j];
Trans2d[0][i][j]=Trans2d[0][i][j-1];
Trans2d[0][i][j-1]=tmp;
}
else
{DEBUG("== It seems both threads are HRTS ....So Skip== ");
continue;
}
}
}
return true;
}
else
{
return false;
}
}
}

Not C++ Question...logic one

Dears,

Kindly need to know where the poppedBusPacket fields (buspaclettype, address..) used before calling the coomandqueue.pop function in update () function in MemoryController although it is initialized in the constructor by null