Comments (2)
TM90
commented on September 24, 2024
It was this way because of the software view of the registerfile which is a byte wise addressing scheme. But you are right in this abstraction level in the hardware description it does not make sense.
I will update the debug output to a sane one...
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TM90
commented on September 24, 2024
Closed with branch iss18 and pull request iss18 (New Generator Architecture). Now the address is given shifted by 3 bit
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Related Issues (20)
- onEachAttribute method bugged if the value contains whitespaces HOT 1
- Automatic Generator Loading did not work on Windows HOT 1
- Support for FIFO register
- Register Maximal width is wrongly supported
- compatibility issues anot XML
- TravisCI Build Enviroment
- for repeated externals only create one verilog file HOT 1
- define generation repeated defines
- Register Addresses should not be in the rfg header
- rfg header file name should be given by user
- Hierarchical naming wrong for externel->external structures
- verilog generator fixed offset register width
- More compact register attribute definitions HOT 1
- synthesisable System Verilog SW Interface
- Counter with clear signal
- Add RTF generator
- Support of new rf macros in e-generator
- hardware ro clear generation fails
- add scala menu generator
- removing group address from html generator
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