unihd-cag/odfi-rfg

TCL based extensible Register File Generator

odfi-rfg's Issues

address aligner

Update the addressing scheme to allow aligning parts of the registerfile to a defined address.

wo field trigger

Also add a register field if it is write only and has a trigger ID

hardware_rreinit

A rreinit_source register triggered from the hardware interface

VerilogGenerator do not generatre hardware description for no rights

If a register has no software and hardware rights do not generate anything

Verilog Generator not writing any data

I found some issues in the VerilogInterface module for Verilog generator.
Maybe they are linked to non-committed code because the sources are not correct.

I committed a few preview fixes on the associated branch

Confusing Address Map in generated verilog code

The address map in the generated files is confusing. Since the 3 least significant bits are discarded through 8-byte granularity the actual address that must be applied is the currently calculated address shifted right by 3bit.

Hope the request is clear :)

General Generator Architecture

Example config file:

package require rfg
package require generator

read_rf info.rf

generator verilog {
    destination_file = ""

}

generator e {
        dest...
}

parameter for external registerfiles

Write a parameter.tm which allows adding parameters to external registerfiles, to define which one the registerfile wants and which ones are required or optional.

Loop variable rfs_to_rfg

Variables in loop statements are converted wrong (missing $) in the rfs_to_rfg conversion tool.

e language generator

Generate e language files for the register file testbench.

Generate 2 files:

• reference modell of the register file
• connect module between uvc and reference modell

Defines TWIDTH

create TWIDTH define in rfgheader generator

refactor VerilogGenerator Helperfunctions

orginise the helper functions in classes.

internal RegisterFiles

Generate internal Registerfiles with the verilog-generator

Description:

registerFile test_rf {
   internal test_extern_rf.rf externRF
}

should be generated as internal instance

Confusing bit-range in signals within RF

Example: address width to a specific RF is 4 bits. In the RF the signal is defined as address[6:3] instead of [3:0].

address calculation bug

In the address calculation the block ids do not influence the object size which leads to wrong calculated addresses in depth hierarchical rf designs

Defines full names

Hierarchical name bug in the rfgheader generator.

Generate repeat block internally as array

Repeat should generate the repetitive part of the register files as an array or like an array.

This is for easier usage in generated testbench/ library code

Generator C/C++ Defines

Create a generator which generates C/C++ Defines for software to support accessing the registerfile from C/C++ Code:

The defines should be like:

#define register_name0 0x000
#define register_name1 0x008
...

But maybe there is a better solution than C/C++ #defines

unit-test environment

A tcl script which searches the unit test folder for *.unit-test.tcl files, and runs them.
For this each unit-test tcl file should be renamed to name.unit-test.tcl as an identifier.

Fixed Address Offset in the registerfile_template

Line 320 in registerfile_template.tcl

Non Vector read_data, write_data, address signals

1 bit wide read_data, write_data and address signals in Register Files are causing errors

Enhanced counters

• Do an evaluation of counters an their functionality.
• Maybe add match signals or a overflow signal to the hardware interface

software ro/wo invalid_address behavior

The behavior of the invalid_address signal should be modified.

More to a invalid_access behavior

better html documentation generator

Create a html documentation with a better overview and navigation within the registerfile documentation

VerilogGenerator read data, write data different width

Generate the write data and read data width with the widht needed and not with the same width

Cleanup package require for ITCL and set to accept v.3.4 and 4.00

TCL 8.6 comes with ITCL 4 per default, and all the package require Itcl 3.4 commands break compatibility.
Cleaning up the requires and enabling ITCL 3.4 and 4.0 will improve general compatibility, and make the tool usable on windows for example

refactoring register file verilog generator

Refactor the register file verilog generator in three steps:

• tcl verilog interface (to hide verilog syntax specifics)
• evaluate generall registerfile structure and change the register file verilog generator to it
• use small functions instead of variable and if structure

Single Register in RF Hierarchie

Single Register RF is causing a verilog error in the hierarchie

RegisterFile with one RAM and software rw permission causes verilog error

If you are generating a registerfile with just one RAM and software rw access and no hardware rights, the output verilog will have a syntax error because of a comma error in the blackbox definition.

.rf description causing the error:

registerFile ramRF {
    ramBlock TestRAM {
        width 16
        depth 32
        software rw
    }
}

Reserved Naming Issue

More than one Reserved Field in one Register results in a naming issue

no ifdef in generated verilog

Hardware dependent features should be implemented via the registerfile description.
(Especially async and sync reset)...

Remove invalid address (and perhaps the address itself?) for single reg RF

Empty always blocks

At the moment there are some cases, where the verilog generator generates empty always blocks, these cases have to be eliminated.

Wrong Calculation for RWIDTH and WWIDTH defines

ones and zero statement for fields

ones and zeros statements for a complete reset to a vector of the field length with ones or zeroes.

Issue for external RamBlock which should act as fifo

external RamBlocks which schould act as fifo results in an error

Adding relative addresses as Attribute

relative addresses should be calculated within the addressing step and added as an attribute...

script to read in verilog defines

A little script which reads in verilog defines as tcl variables.
This can be handy for the generation of registerfiles with parameter.

Invalid Address Signal for write operation

Depending of the definition on when the invalid address signal should appear there may is a bug in the hardware generation for write only registerfile objects. (To be confirmed...)

external ramBlocks

Add generation of external ramBlocks in the verilog-generator.

Description:

ramBlock RAM {
    external
    width 16
    depth 256 
    software rw
    hardware rw
}

Will generate input and outputs for an external ramBlock.

System Verilog Generator

A Generator to produce files for the system verilog software interafce of the RFG.

VerilogGenerator Specification

A document in which is defined which RFG description results in which hardware

e generator for hw interface

generator for e, which builds a top.e file for the hw interface of the register file. In this file an UVC is instantiated for each field/ramblock of the register file.

Interrupt Trigger Enable

For an external Trigger block trigger signals should be generated when they are not existing:

register r1 {
    field f1 {
        width 1
        hardware {
            rw
            trigger "TriggerID"
        }
    }
}

Also the triggers should have IDs trigger with the same ID should be ored in an hierarchical way

edge triggered counter

Add an attribute for counters to let them count on a rising edge...

rfsbackport cannot handle groups

rfs backport tries to read out the absolute address of a group which does not exist and then crashes.

Dead trigger signal

fields for ramBlocks

verilog generation for ramBlocks with fields.

How it should be generated has to be defined.

Multi-bit Counter

Add parameter to RF counter to increment by more than one

VerilogGenerator: Wire/Reg for external Rams

wire and regs for the signals in the VerilogGenerator may are not generated correctly for external RAMs in use with internal RegisterFiles