v0idv0id/stm32-scaler

A simple timer PSC, ARR and CCRx calculator for STM32 MCUs

stm32-scaler's Issues

Round CRRx to nearest instead of round by chop for smaller error

Nice script! I have a small improvement.

STM32-Scaler/timscale.py

Line 108 in 4671486

d = int(arr/(100.0/DUTY))

If you replace d = int(arr/(100.0/DUTY)) by d = int(arr/(100.0/DUTY)+0.5) the error in the duty cycle could get smaller :)
And than you have to do minus 1 probably, never mind. I think it's good after all.

Might miss a better result sometimes

Hi, didn't quite understand why you would require the chips frequency to be divisible by the prescaler when there can't be a perfect solution anyways and we have to accept an error. From what I understood a prescaler value of N basically results in the counter being counted ( and reset/triggered on ARR) only every Nth cycle, so what we really are looking for is a good PSC*ARR combination for the desired amount of cycles.
I compared the output of this script with some others and found that for

timescale.py -t 0.007777 -c 22180400 -e 0.1

only when I change the if to

if ( (TIM_BASE_CLOCK % (psc+1) == 0) or (psc==2) ) and x <= TARGET_ARR_MAX[bit]:

I will get a near perfect match of

PSC: 2 ARR: 57498 => FREQ: 128.58426523359827 [Hz] ERROR: 1.6927833490498756e-05 [%] - CRRx[ 50.0 %]: 28749
PSC: 3 ARR: 43123 => FREQ: 128.585010666914 [Hz] ERROR: 0.000562792491631825 [%] - CRRx[ 50.0 %]: 21561

which results in the desired frequncy to only have a tiny bit of error to the clock frequency (357499128.5842870001286 = 22180403.75) whereas the next best only gets near to 22180275 ... probably not relevant in realy life applications but I was wondering if there might be cases where this would miss really much better ones...