viktor-nikolov/microblaze-ddr3-tutorial

Tutorial of a HW design of MicroBlaze using DDR3 RAM on Arty A7 board; DDR3 RAM speed test application

microblaze-ddr3-tutorial's Issues

Errors produced after running implementation. Should I ignore?

The following message is generated after I finish running "implementation", and causes me to unable to generate bitstream. I dont know how to read these message. I have already set main clock clk_wiz_0.clk_out1 to 100 MHz as mentioned

design_1
General Messages
[IP_Flow 19-1747] Failed to deliver file 's:/Xilinx/Vivado/2023.1/data/ip/xilinx/mig_7series_v4_2/xit/synthesis.xit': error renaming "s:/Xilinx/Projects/matrix_multiplication_engine/matrix_multiplication_engine.gen/sources_1/bd/design_1/ip/design_1_mig_7series_0_4/_tmp/design_1_mig_7series_0_4" to "s:/Xilinx/Projects/matrix_multiplication_engine/matrix_multiplication_engine.gen/sources_1/bd/design_1/ip/design_1_mig_7series_0_4/design_1_mig_7series_0_4": permission denied

[IP_Flow 19-167] Failed to deliver one or more file(s).

[IP_Flow 19-3505] IP Generation error: Failed to generate IP 'mig_7series_0'. Failed to generate 'Synthesis' outputs: 

[IP_Flow 19-98] Generation of the IP CORE failed.
Failed to generate IP 'mig_7series_0'. Failed to generate 'Synthesis' outputs: 

[BD 41-1030] Generation failed for the IP Integrator block mig_7series_0 

[Vivado 12-4756] Launch of runs aborted due to earlier errors while preparing sub-designs for run execution.

synth_1
General Messages
[Netlist 29-160] Cannot set property 'IOSTANDARD', because the property does not exist for objects of type 'pin'. ["s:/Xilinx/Projects/matrix_multiplication_engine/matrix_multiplication_engine.gen/sources_1/bd/design_1/ip/design_1_mig_7series_0_4/design_1_mig_7series_0_4/user_design/constraints/design_1_mig_7series_0_4.xdc":275]

[Common 17-55] 'set_property' expects at least one object. ["S:/Xilinx/Projects/matrix_multiplication_engine/matrix_multiplication_engine.srcs/constrs_1/imports/Downloads/Arty-A7-100-Master.xdc":138]

Implementation
Design Initialization
[Netlist 29-160] Cannot set property 'IOSTANDARD', because the property does not exist for objects of type 'pin'. ["s:/Xilinx/Projects/matrix_multiplication_engine/matrix_multiplication_engine.gen/sources_1/bd/design_1/ip/design_1_mig_7series_0_4/design_1_mig_7series_0_4/user_design/constraints/design_1_mig_7series_0_4.xdc":275]

[Common 17-55] 'set_property' expects at least one object. ["S:/Xilinx/Projects/matrix_multiplication_engine/matrix_multiplication_engine.srcs/constrs_1/imports/Downloads/Arty-A7-100-Master.xdc":138]

Write Bitstream
DRC
Pin Planning
[DRC NSTD-1] Unspecified I/O Standard: 1 out of 53 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: clk_a0[0].

[DRC UCIO-1] Unconstrained Logical Port: 1 out of 53 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: clk_a0[0].

Implementation
Routing
  Routing Resources
   Backbone
     [DRC RTRES-1] Backbone resources: 1 net(s) have CLOCK_DEDICATED_ROUTE set to BACKBONE but do not use backbone resources. The problem net(s) are design_1_i/util_ds_buf_0/U0/BUFG_O[0].

[Vivado 12-1345] Error(s) found during DRC. Bitgen not run.

Memory write error at 0x80000000. MicroBlaze instruction insert overrun

Hello,
First of all, thanks for your tutorial, it's great and easy to follow.
I followed it using an Arty 100 instead of the Arty 35 and everything seemed to work fine. However, when I try to run the program the following error appears:
10:05:47 ERROR : Memory write error at 0x80000000. MicroBlaze instruction insert overrun

I checked the Vitis Log and this is it in case you need it:

10:04:56 INFO	: Checking for BSP changes to sync application flags for project 'DDR3_read_test'...
10:05:27 INFO	: Bit file 'C:/workspace/DDR3_read_test/_ide/bitstream/download.bit' is generated.
10:05:27 INFO	: Connected to target on host '127.0.0.1' and port '3121'.
10:05:27 INFO	: 'targets -set -filter {jtag_cable_name =~ "Digilent USB104 A7 - 100T 210398AE9417A" && level==0 && jtag_device_ctx=="jsn-USB104 A7 - 100T-210398AE9417A-13631093-0"}' command is executed.
10:05:29 INFO	: Device configured successfully with "C:/workspace/DDR3_read_test/_ide/bitstream/download.bit"
10:05:41 INFO	: Connected to target on host '127.0.0.1' and port '3121'.
10:05:42 INFO	: Jtag cable 'Digilent USB104 A7 - 100T 210398AE9417A' is selected.
10:05:42 INFO	: 'jtag frequency' command is executed.
10:05:42 INFO	: 'targets -set -filter {jtag_cable_name =~ "Digilent USB104 A7 - 100T 210398AE9417A" && level==0 && jtag_device_ctx=="jsn-USB104 A7 - 100T-210398AE9417A-13631093-0"}' command is executed.
10:05:44 INFO	: Device configured successfully with "C:/workspace/DDR3_read_test/_ide/bitstream/system_wrapper_leds.bit"
10:05:44 INFO	: Context for processor 'microblaze_0' is selected.
10:05:44 INFO	: Hardware design and registers information is loaded from 'C:/workspace/system/export/system/hw/system_wrapper_leds.xsa'.
10:05:44 INFO	: 'configparams mdm-detect-bscan-mask 2' command is executed.
10:05:44 INFO	: Context for processor 'microblaze_0' is selected.
10:05:44 INFO	: System reset is completed.
10:05:47 INFO	: 'after 3000' command is executed.
10:05:47 INFO	: Context for processor 'microblaze_0' is selected.
10:05:47 ERROR	: Memory write error at 0x80000000. MicroBlaze instruction insert overrun
10:05:47 INFO	: ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
targets -set -filter {jtag_cable_name =~ "Digilent USB104 A7 - 100T 210398AE9417A" && level==0 && jtag_device_ctx=="jsn-USB104 A7 - 100T-210398AE9417A-13631093-0"}
fpga -file C:/workspace/DDR3_read_test/_ide/bitstream/system_wrapper_leds.bit
targets -set -nocase -filter {name =~ "*microblaze*#0" && bscan=="USER2" }
loadhw -hw C:/workspace/system/export/system/hw/system_wrapper_leds.xsa -regs
configparams mdm-detect-bscan-mask 2
targets -set -nocase -filter {name =~ "*microblaze*#0" && bscan=="USER2" }
rst -system
after 3000
targets -set -nocase -filter {name =~ "*microblaze*#0" && bscan=="USER2" }
dow C:/workspace/DDR3_read_test/Debug/DDR3_read_test.elf
----------------End of Script----------------

I checked online and I saw it could be something related to the timing constraints, so I checked the Vivado timing report summary and i got this:

Is there anything I could change in order to work properly?
Thank you in advance

Bitstream generation failed

Hi

I followed your tutorial using the Nexys A7 board. I connected ck_rt to the CPU RESET button on the board by uncommenting the following line in the xdc file,

##CPU Reset Button
set_property -dict { PACKAGE_PIN C12   IOSTANDARD LVCMOS33 } [get_ports { ck_rst }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn

That solved the first error but what I'm unclear about is the role of ck_a0[0] that remains unconstrained & the Nexys 7 xdc doesn't appear to have an equivalent pin to assign. Can I just uncomment one of the Pmod header pins?

##Pmod Headers
##Pmod Header JA
#set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS33 } [get_ports { JA[1] }]; #IO_L20N_T3_A19_15 Sch=ja[1]
......
......
......