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License: Other

Shell 0.02% CSS 1.65% HTML 42.82% Makefile 0.01% PHP 3.37% SourcePawn 0.27% Java 46.70% JavaScript 0.57% Verilog 0.27% Python 0.03% Dockerfile 0.01% Hack 0.68% Raku 3.63%
ph2-lab iiith vlsi-iiith

vlsi-iiith's Introduction

Congrats !!

* You have successfully downloaded and extracted the
  ui.tgz .


* Changes: New Tabs have been added for 
	-    Target Audience
	-    Courses Aligned
	-    Pre-requisite Softwares 

You need to added 3 more sections on virtual lab home page

3) Target Audience
4) Courses Aligned
5) Pre-requisite Softwares

You can make the above said changes by editing content.html. To update the changes

1)  open content.html in your fav editor and search for last closing html tag </section>.
2) Open the change.html file and open it in your fav. editor.
3) Copy all content of change.html 
4) Paste it after the last closing html tag </section> (you searched in Step1).
5) Go to ui/src and run  " make theme=blue-icon"     on command terminal  to change theme to blue


We had attached change.html in folder.  You can copy the whole content and paste it in content.html .


Below is snapshot how content.html will look like
<!-- Second section of the article-->
<section id="lab-article-section-2">

<div id="lab-article-section-2-icon" class="icon">
  <!-- Enclose the icon image for the section. -->
  <img src="images/simulation.jpg" />
</div>


<!-- The heading for the section can be enclosed in a 
div tag and shown with a <h2> tag -->
<div id="lab-article-section-2-heading" class="heading">
  List of experiments
</div>
			
<!-- Write the section content inside a paragraph 
element, You can also include images with <img> tag -->
<div id="lab-article-section-2-content" class="content">
  <ul id="list-of-experiments">
  
    <li> 
      <!--Link and name of the experiment 1 -->
      <a href="exp1/index.html">Simple Pendulum Experiment</a> 
    </li>
  </ul>
</div>

</section>

// PASTE the CHANGE.html content here..


/*****************************************************************/









* Now run makefile by the following commands inside the 'ui/src' folder to
  change the default theme :

Go to Command Terminal
	 $ cd ui_extracted_folder // Where u have extracted the ui kit
	 $ cd ui/src
         $ make clean all 
	 $ make theme=blue-icon

* Now, open ui/build/index.html in the browser to test the template.

vlsi-iiith's People

Contributors

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vlsi-iiith's Issues

QA_Delay Estimation In Chain Of Inverters_Post-Quiz_p1

Defect Description :
In the quiz page of "Delay Estimation In Chain Of Inverters" experiment, for the post quiz, the cancel button is not present in the page instead the cancel button should be displayed on the screen as to unselect the selected radio buttons

Actual Result :
In the quiz page of "Delay Estimation In Chain Of Inverters" experiment, for the post quiz, the cancel button is not present in the page

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Delay%20Estimation%20In%20Chain%20Of%20Inverters/Delay%20Estimation%20In%20Chain%20Of%20Inverters_20_Post-Quiz_p1.org

Attachment:
37

QA_Schematic Design Of D-Latch and D-Flip Flop_Usability_smk

Defect Description :
In the landing page/home page of "Schematic Design Of D-Latch and D-Flip Flop" experiment, the name of the experiment is not present in the screen instead the experiment name should be displayed on the screen at the top of the header options

Actual Result :
In the landing page/home page of "Schematic Design Of D-Latch and D-Flip Flop" experiment, the name of the experiment is not present in the screen

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Schematic%20Design%20Of%20D-Latch%20and%20D-Flip%20Flop/Schematic%20Design%20Of%20D-Latch%20and%20D-Flip%20Flop_01_Usability_smk.org

Attachment:
33

QA_Schematic Design Of Pass Transistor Logic & Multiplexer_Feedback_smk

Defect Description :
In the feedback page of "Schematic Design Of Pass Transistor Logic & Multiplexer" experiment,the cancel button is not present in the page instead the cancel button should be displayed on the screen as to unselect the selected radio buttons

Actual Result :
In the feedback page of "Schematic Design Of Pass Transistor Logic & Multiplexer" experiment,the cancel button is not present in the page

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Schematic%20Design%20Of%20Pass%20Transistor%20Logic%20%26%20Multiplexer/Schematic%20Design%20Of%20Pass%20Transistor%20Logic%20%26%20Multiplexer_30_Feedback_smk.org
Attachment:
43

QA_Layout Design_Back to experiment_smk

Defect Description :
In the "Layout Design" experiment,the back to experiments link is not present in the page instead the back to experiments link should be displayed on the screen inorder to view the list of experiments by the user

Actual Result :
In the "Layout Design" experiment,the back to experiments link is not present in the page

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Layout%20Design/Layout%20Design_27_Back%20to%20experiment_smk.org

Attachment;
2

QA_Delay Estimation In Chain Of Inverters_Feedback_p1

Defect Description :
In the feedback page of "Delay Estimation In Chain Of Inverters" experiment,when we click on submit button with out entering the data in the corresponding fields an successful message is displayed on the screen instead an error message should be displayed on the screen as to enter the data in the corresponding fields

Actual Result :
In the feedback page of "Delay Estimation In Chain Of Inverters" experiment,when we click on submit button with out entering the data in the corresponding fields an successful message is displayed on the screen

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Delay%20Estimation%20In%20Chain%20Of%20Inverters/Delay%20Estimation%20In%20Chain%20Of%20Inverters_28_Feedback_p1.org

Attachment:
35

QA_Spice Code Platform_Feedback_smk

Defect Description :
In the feedback page of "Spice Code Platform" experiment,the cancel button is not present in the page instead the cancel button should be displayed on the screen as to unselect the selected radio buttons

Actual Result :
In the feedback page of "Spice Code Platform" experiment,the cancel button is not present in the page

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Spice%20Code%20Platform/Spice%20Code%20Platform_21_Feedback_smk.org

Attachment:
23

QA_Delay Estimation In Chain Of Inverters_Feedback_smk

Defect Description :
In the feedback page of "Delay Estimation In Chain Of Inverters" experiment,the cancel button is not present in the page instead the cancel button should be displayed on the screen as to unselect the selected radio buttons

Actual Result :
In the feedback page of "Delay Estimation In Chain Of Inverters" experiment,the cancel button is not present in the page

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Delay%20Estimation%20In%20Chain%20Of%20Inverters/Delay%20Estimation%20In%20Chain%20Of%20Inverters_25_Feedback_smk.org

Attachment:
36

No output color change after simulation.

Defect Description:
In the D flip-flop design experiment, When we simulate the circuit, the output of the circuit should change as per the boolean value.

Defect Description:
In the D flip-flop design experiment, When we simulate the circuit, it start downloading the file, but the color of the element output does not change.

Environment :
OS: Windows 7, Ubuntu-16.04,Centos-6
Browsers: Firefox-42.0,Chrome-47.0,chromium-45.0
Bandwidth : 100Mbps
Hardware Configuration:4GBRAM ,
Processor:i5

Reported by: @rohita323 @rajat974 @divvy81

QA_Design Of D-Flip Flop Using Verilog_Usability_smk

Defect Description :
In the landing page/home page of "Design Of D-Flip Flop Using Verilog" experiment, the name of the experiment is not present in the screen instead the experiment name should be displayed on the screen at the top of the header options

Actual Result :
In the landing page/home page of "Design Of D-Flip Flop Using Verilog" experiment, the name of the experiment is not present in the screen

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Design%20Of%20D-Flip%20Flop%20Using%20Verilog/Design%20Of%20D-Flip%20Flop%20Using%20Verilog_01_Usability_smk.org

Attachment:
20

QA_Design Of D-Flip Flop Using Verilog_Feedback_p1

Defect Description :
In the feedback page of "Design Of D-Flip Flop Using Verilog" experiment,when we click on submit button with out entering the data in the corresponding fields an successful message is displayed on the screen instead an error message should be displayed on the screen as to enter the data in the corresponding fields

Actual Result :
In the feedback page of "Design Of D-Flip Flop Using Verilog" experiment,when we click on submit button with out entering the data in the corresponding fields an successful message is displayed on the screen

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Design%20Of%20D-Flip%20Flop%20Using%20Verilog/Design%20Of%20D-Flip%20Flop%20Using%20Verilog_27_Feedback_p1.org

Attachment:
16

QA_Schematic Design Of D-Latch and D-Flip Flop_Post-Quiz_p1

Defect Description :
In the quiz page of "Schematic Design Of D-Latch and D-Flip Flop" experiment, for the post quiz, the cancel button is not present in the page instead the cancel button should be displayed on the screen as to unselect the selected radio buttons

Actual Result :
In the quiz page of "Schematic Design Of D-Latch and D-Flip Flop" experiment, for the post quiz, the cancel button is not present in the page

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Schematic%20Design%20Of%20D-Latch%20and%20D-Flip%20Flop/Schematic%20Design%20Of%20D-Latch%20and%20D-Flip%20Flop_24_Post-Quiz_p1.org

Attachment:

30

QA_Design Of D-Flip Flop Using Verilog_Feedback_smk

Defect Description :
In the feedback page of "Design Of D-Flip Flop Using Verilog" experiment,the cancel button is not present in the page instead the cancel button should be displayed on the screen as to unselect the selected radio buttons

Actual Result :
In the feedback page of "Design Of D-Flip Flop Using Verilog" experiment,the cancel button is not present in the page

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Design%20Of%20D-Flip%20Flop%20Using%20Verilog/Design%20Of%20D-Flip%20Flop%20Using%20Verilog_24_Feedback_smk.org

Attachment:
17

QA_Delay Estimation In Chain Of Inverters_Back to experiment_smk

Defect Description :
In the "Delay Estimation In Chain Of Inverters" experiment,the back to experiments link is not present in the page instead the back to experiments link should be displayed on the screen inorder to view the list of experiments by the user

Actual Result :
In the "Delay Estimation In Chain Of Inverters" experiment,the back to experiments link is not present in the page

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Delay%20Estimation%20In%20Chain%20Of%20Inverters/Delay%20Estimation%20In%20Chain%20Of%20Inverters_30_Back%20to%20experiment_smk.org

Attachment:
34

QA_Schematic Design Of D-Latch and D-Flip Flop_Feedback_p1

Defect Description :
In the feedback page of "Schematic Design Of D-Latch and D-Flip Flop" experiment,when we click on submit button with out entering the data in the corresponding fields an successful message is displayed on the screen instead an error message should be displayed on the screen as to enter the data in the corresponding fields

Actual Result :In the feedback page of "Schematic Design Of D-Latch and D-Flip Flop" experiment,when we click on submit button with out entering the data in the corresponding fields an successful message is displayed on the screen

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Schematic%20Design%20Of%20D-Latch%20and%20D-Flip%20Flop/Schematic%20Design%20Of%20D-Latch%20and%20D-Flip%20Flop_32_Feedback_p1.org

Attachment:
28

QA_Schematic Design Of Pass Transistor Logic & Multiplexer_Post-Quiz_p1

Defect Description :
In the quiz page of "Schematic Design Of Pass Transistor Logic & Multiplexer" experiment, for the post quiz, the cancel button is not present in the page instead the cancel button should be displayed on the screen as to unselect the selected radio buttons

Actual Result :
In the quiz page of "Schematic Design Of Pass Transistor Logic & Multiplexer" experiment, for the post quiz, the cancel button is not present in the page

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Schematic%20Design%20Of%20Pass%20Transistor%20Logic%20%26%20Multiplexer/Schematic%20Design%20Of%20Pass%20Transistor%20Logic%20%26%20Multiplexer_25_Post-Quiz_p1.org

Attachment:
44

QA_Layout Design_feedback_p1

Defect Description :
In the feedback page of "Layout Design" experiment,when we click on submit button with out entering the data in the corresponding fields an successul message is displayed on the screen instead an error message should be displayed on the screen as to enter the data in the corresponding fields

Actual Result :
In the feedback page of "Layout Design" experiment,when we click on submit button with out entering the data in the corresponding fields an successul message is displayed on the screen

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Layout%20Design/Layout%20Design_25_feedback_p1.org

Attachment:
3

QA_Spice Code Platform_Back to experiment_smk

Defect Description :
In the "Spice Code Platform" experiment,the back to experiments link is not present in the page instead the back to experiments link should be displayed on the screen inorder to view the list of experiments by the user

Actual Result :
In the "Spice Code Platform" experiment,the back to experiments link is not present in the page

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Spice%20Code%20Platform/Spice%20Code%20Platform_26_Back%20to%20experiment_smk.org

Attachment:
21

QA_Spice Code Platform_Usability_smk

Defect Description :
In the landing page/home page of "Spice Code Platform" experiment, the name of the experiment is not present in the screen instead the experiment name should be displayed on the screen at the top of the header options

Actual Result :
In the landing page/home page of "Spice Code Platform" experiment, the name of the experiment is not present in the screen

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Spice%20Code%20Platform/Spice%20Code%20Platform_01_Usability_smk.org

Attachment:
26

QA_Schematic Design Of D-Latch and D-Flip Flop_Feedback_smk

Defect Description :
In the feedback page of "Schematic Design Of D-Latch and D-Flip Flop" experiment,the cancel button is not present in the page instead the cancel button should be displayed on the screen as to unselect the selected radio buttons

Actual Result :
In the feedback page of "Schematic Design Of D-Latch and D-Flip Flop" experiment,the cancel button is not present in the page

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Schematic%20Design%20Of%20D-Latch%20and%20D-Flip%20Flop/Schematic%20Design%20Of%20D-Latch%20and%20D-Flip%20Flop_29_Feedback_smk.org

Attachment:
29

QA_Design Of Digital Circuits Using Verilog_Usability_smk

Defect Description :
In the landing page/home page of "Design Of Digital Circuits Using Verilog" experiment, the name of the experiment is not present in the screen instead the experiment name should be displayed on the screen at the top of the header options

Actual Result :
In the landing page/home page of "Design Of Digital Circuits Using Verilog" experiment, the name of the experiment is not present in the screen

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Design%20Of%20Digital%20Circuits%20Using%20Verilog/Design%20Of%20Digital%20Circuits%20Using%20Verilog_01_Usability_smk.org

Attachment:
14

QA_Schematic Design Of D-Latch and D-Flip Flop_Usability_smk

Defect Description :
In the home page/landing page of "Schematic Design Of D-Latch and D-Flip Flop" experiment, an extra header link is present in the page where the extra header link should be removed as it is not required

Actual Result :
In the home page/landing page of "Schematic Design Of D-Latch and D-Flip Flop" experiment, an extra header link is present in the page

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Schematic%20Design%20Of%20D-Latch%20and%20D-Flip%20Flop/Schematic%20Design%20Of%20D-Latch%20and%20D-Flip%20Flop_01_Usability_smk.org

Attachment:
32

Incomplete database file

This lab runs as a database application. In the process of Integration we discovered that the database file checked in the sources is not the one currently running on IIIT-H server. We got to know that the lab is pointing to db.virtual-labs.ac.in which is running on base3 machine. We have exported the current running database and tried to run it on my local machine. When I process this sql file to import it neither throws an error nor returns the control back.

Thanks and Regards

QA_Design Of Digital Circuits Using Verilog_Back to experiment_smk

Defect Description :
In the "Design Of Digital Circuits Using Verilog" experiment,the back to experiments link is not present in the page instead the back to experiments link should be displayed on the screen inorder to view the list of experiments by the user

Actual Result :
In the "Design Of Digital Circuits Using Verilog" experiment,the back to experiments link is not present in the page

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Design%20Of%20Digital%20Circuits%20Using%20Verilog/Design%20Of%20Digital%20Circuits%20Using%20Verilog_27_Back%20to%20experiment_smk.org

Attachment:
9

QA_Delay Estimation In Chain Of Inverters_Pre-Quiz_p1

Defect Description :
In the virtual experiment page of "Delay Estimation In Chain Of Inverters" experiment, for the pre quiz, the cancel button is not present in the page instead the cancel button should be displayed on the screen as to unselect the selected radio buttons

Actual Result :
In the virtual experiment page of "Delay Estimation In Chain Of Inverters" experiment, for the pre quiz, the cancel button is not present in the page

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Delay%20Estimation%20In%20Chain%20Of%20Inverters/Delay%20Estimation%20In%20Chain%20Of%20Inverters_10_Pre-Quiz_p1.org

Attachment:
38

QA_Delay Estimation In Chain Of Inverters_Usability_smk

Defect Description :
In the landing page/home page of "Delay Estimation In Chain Of Inverters" experiment, the name of the experiment is not present in the screen instead the experiment name should be displayed on the screen at the top of the header options

Actual Result :
In the landing page/home page of "Delay Estimation In Chain Of Inverters" experiment, the name of the experiment is not present in the screen

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Delay%20Estimation%20In%20Chain%20Of%20Inverters/Delay%20Estimation%20In%20Chain%20Of%20Inverters_01_Usability_smk.org

Attachment:
40

QA_System_Feedback_smk

Defect Description :
In the home page of "VLSI" Lab,when we click on the feedback link it is redirecting to an error page(404) instead feedback page should get opened

Actual Result :
In the home page of "VLSI" Lab,when we click on the feedback link it is redirecting to an error page(404)

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/System/System_06_Feedback_smk.org

Attachment:
1

QA_Design Of Digital Circuits Using Verilog_feedback_smk

Defect Description :
In the feedback page of "Design Of Digital Circuits Using Verilog" experiment,the cancel button is not present in the page instead the cancel button should be displayed on the screen as to unselect the selected radio buttons

Actual Result :
In the feedback page of "Design Of Digital Circuits Using Verilog" experiment,the cancel button is not present in the page

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Design%20Of%20Digital%20Circuits%20Using%20Verilog/Design%20Of%20Digital%20Circuits%20Using%20Verilog_21_feedback_smk.org\

Attachment:
11

QA_Schematic Design Of Pass Transistor Logic & Multiplexer_Usability_smk

Defect Description :
In the home page/landing page of "Schematic Design Of Pass Transistor Logic & Multiplexer" experiment, an extra header link is present in the page where the extra header link should be removed as it is not required

Actual Result :
In the home page/landing page of "Schematic Design Of Pass Transistor Logic & Multiplexer" experiment, an extra header link is present in the page

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Schematic%20Design%20Of%20Pass%20Transistor%20Logic%20%26%20Multiplexer/Schematic%20Design%20Of%20Pass%20Transistor%20Logic%20%26%20Multiplexer_01_Usability_smk.org
Attachment:
46

QA_Design Of D-Flip Flop Using Verilog_Usability_smk

Defect Description :
In the home page/landing page of "Design Of D-Flip Flop Using Verilog" experiment, an extra header link is present in the page where the extra header link should be removed as it is not required

Actual Result :
In the home page/landing page of "Design Of D-Flip Flop Using Verilog" experiment, an extra header link is present in the page

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Design%20Of%20D-Flip%20Flop%20Using%20Verilog/Design%20Of%20D-Flip%20Flop%20Using%20Verilog_01_Usability_smk.org

Attachment:
19

QA_Schematic Design Of Pass Transistor Logic & Multiplexer_Pre-Quiz_p1

Defect Description :
In the virtual experiment page of "Schematic Design Of Pass Transistor Logic & Multiplexer" experiment, for the pre quiz, the cancel button is not present in the page instead the cancel button should be displayed on the screen as to unselect the selected radio buttons

Actual Result :
In the virtual experiment page of "Schematic Design Of Pass Transistor Logic & Multiplexer" experiment, for the pre quiz, the cancel button is not present in the page

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Schematic%20Design%20Of%20Pass%20Transistor%20Logic%20%26%20Multiplexer/Schematic%20Design%20Of%20Pass%20Transistor%20Logic%20%26%20Multiplexer_10_Pre-Quiz_p1.org
Attachment:
45

QA_Design Of D-Flip Flop Using Verilog_Post-Quiz_p1

Defect Description :
In the quiz page of "Design Of D-Flip Flop Using Verilog" experiment, for the post quiz, the cancel button is not present in the page instead the cancel button should be displayed on the screen as to unselect the selected radio buttons

Actual Result :
In the quiz page of "Design Of D-Flip Flop Using Verilog" experiment, for the post quiz, the cancel button is not present in the page

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Design%20Of%20D-Flip%20Flop%20Using%20Verilog/Design%20Of%20D-Flip%20Flop%20Using%20Verilog_19_Post-Quiz_p1.org

Attachment:
18

QA_Layout Design_Usability_smk

Defect Description :
In the landing page/home page of "Layout Design" experiment, the name of the experiment is not present in the screen instead the experiment name should be displayed on the screen at the top of the header options

Actual Result :
In the landing page/home page of "Layout Design" experiment, the name of the experiment is not present in the screen

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Layout%20Design/Layout%20Design_01_Usability_smk.org

Attachment:
8

QA_Design Of Digital Circuits Using Verilog_Usability_smk

Defect Description :
In the home page/landing page of "Design Of Digital Circuits Using Verilog" experiment, an extra header link is present in the page where the extra header link should be removed as it is not required

Actual Result :
In the home page/landing page of "Design Of Digital Circuits Using Verilog" experiment, an extra header link is present in the page

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Design%20Of%20Digital%20Circuits%20Using%20Verilog/Design%20Of%20Digital%20Circuits%20Using%20Verilog_01_Usability_smk.org

Attachment:
13

QA_Layout Design_Usability_smk

Defect Description :
In the home page/landing page of "Layout Design" experiment, an extra header link is present in the page where the extra header link should be removed as it is not required

Actual Result :
In the home page/landing page of "Layout Design" experiment, an extra header link is present in the page

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Layout%20Design/Layout%20Design_01_Usability_smk.org

Attachment:
7

QA_Design Of Digital Circuits Using Verilog_Post-Quiz_p1

Defect Description :
In the quiz page of "Design Of Digital Circuits Using Verilog" experiment, for the post quiz, the cancel button is not present in the page instead the cancel button should be displayed on the screen as to unselect the selected radio buttons

Actual Result :
In the quiz page of "Design Of Digital Circuits Using Verilog" experiment, for the post quiz, the cancel button is not present in the page

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Design%20Of%20Digital%20Circuits%20Using%20Verilog/Design%20Of%20Digital%20Circuits%20Using%20Verilog_16_Post-Quiz_p1.org

Attachment:
12

QA_Schematic Design Of Pass Transistor Logic & Multiplexer_Feedback_p1

Defect Description :
In the feedback page of "Schematic Design Of Pass Transistor Logic & Multiplexer" experiment,when we click on submit button with out entering the data in the corresponding fields an successful message is displayed on the screen instead an error message should be displayed on the screen as to enter the data in the corresponding fields

Actual Result :
In the feedback page of "Schematic Design Of Pass Transistor Logic & Multiplexer" experiment,when we click on submit button with out entering the data in the corresponding fields an successful message is displayed on the screen

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Schematic%20Design%20Of%20Pass%20Transistor%20Logic%20%26%20Multiplexer/Schematic%20Design%20Of%20Pass%20Transistor%20Logic%20%26%20Multiplexer_33_Feedback_p1.org

Attachment:
42

QA_Layout Design_Virtual Experiment_p1

Defect Description :
In the virtual experiment page of "Layout Design" experiment,when we click on "pre quiz" link it is redirecting to the error page instead it should redirect to the pre-quiz page.

Actual Result :
In the virtual experiment page of "Layout Design" experiment,when we click on "pre quiz" link it is redirecting to the error page

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Layout%20Design/Layout%20Design_09_Virtual%20Experiment_p1.org

Attachment:
6

QA_Schematic Design Of D-Latch and D-Flip Flop_Pre-Quiz_p1

Defect Description :
In the virtual experiment page of "Schematic Design Of D-Latch and D-Flip Flop" experiment, for the pre quiz, the cancel button is not present in the page instead the cancel button should be displayed on the screen as to unselect the selected radio buttons

Actual Result :
In the virtual experiment page of "Schematic Design Of D-Latch and D-Flip Flop" experiment, for the pre quiz, the cancel button is not present in the page

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Schematic%20Design%20Of%20D-Latch%20and%20D-Flip%20Flop/Schematic%20Design%20Of%20D-Latch%20and%20D-Flip%20Flop_12_Pre-Quiz_p1.org

Attachment:
31

QA_Spice Code Platform_Usability_smk

Defect Description :
In the home page/landing page of "Spice Code Platform" experiment, an extra header link is present in the page where the extra header link should be removed as it is not required

Actual Result :
In the home page/landing page of "Spice Code Platform" experiment, an extra header link is present in the page

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Spice%20Code%20Platform/Spice%20Code%20Platform_01_Usability_smk.org

QA_Spice Code Platform_Feedback_p1

Defect Description :
In the feedback page of "Spice Code Platform" experiment,when we click on submit button with out entering the data in the corresponding fields an successful message is displayed on the screen instead an error message should be displayed on the screen as to enter the data in the corresponding fields

Actual Result :
In the feedback page of "Spice Code Platform" experiment,when we click on submit button with out entering the data in the corresponding fields an successful message is displayed on the screen

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Spice%20Code%20Platform/Spice%20Code%20Platform_24_Feedback_p1.org

Attachment:
22

QA_Spice Code Platform_Post-Quiz_p1

Defect Description :
In the quiz page of "Spice Code Platform" experiment, for the post quiz, the cancel button is not present in the page instead the cancel button should be displayed on the screen as to unselect the selected radio buttons

Actual Result :
In the quiz page of "Spice Code Platform" experiment, for the post quiz, the cancel button is not present in the page
Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Spice%20Code%20Platform/Spice%20Code%20Platform_16_Post-Quiz_p1.org

Attachment:
24

No output generated for D-Flip Flop Positive Edge Triggered

When we click on Simulate button,graph gets generated but the output is a straight line instead of postive edge trigger output of D Flip Flop.

Expected Output:
Similar to D-Flip Flop negative edge triggered simulation output graph, Input should have both high and low signals and output line should show rectangular areas at negative edge of clock based on input at that time.

screenshot1

Environment :
OS: Windows 7,
Browsers: Firefox-43.0.4
Bandwidth : 40Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

@khushpreet-kaur
Submitted by : (Team -7) Subhash Kanuru ,Somya, Simran

Simulation By changing input parameters is not working

In D- Latch, D-Flip Flop Positive Edge Triggered and D-Flip Flop Negative Edge Triggered experiments on changing the input variables simulation graph is not changing accordingly.

Steps to reproduce:

  1. Click(Mouse right click or left click) on the Input component D that is added
  2. A popup gets displayed with variable parameters Min Volt, Max Volt, Step Size, Raise time, Fall time, Total time
  3. Change any of the parameters and click on OK button.
  4. Click on the Simulate button to generate a new graph

Current Result:
No change in the output simulation graph

Expected Result:
A new simulation graph corresponding to changes in the input should be displayed in simulation region.

@khushpreet-kaur
Submitted By : (Team 7) Subhash Kanuru, Somya, Simran

QA_Layout Design_Post-Quiz_p1

Defect Description :
In the quiz page of "Layout Design" experiment, for the post quiz, the cancel button is not present in the page instead the cancel button should be displayed on the screen as to unselect the selected radio buttons

Actual Result :
In the quiz page of "Layout Design" experiment, for the post quiz, the cancel button is not present in the page

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Layout%20Design/Layout%20Design_17_Post-Quiz_p1.org

Attachment:
5

QA_Schematic Design Of Pass Transistor Logic & Multiplexer_Back to experiment_smk

Defect Description :
In the "Schematic Design Of Pass Transistor Logic & Multiplexer" experiment,the back to experiments link is not present in the page instead the back to experiments link should be displayed on the screen inorder to view the list of experiments by the user

Actual Result :
In the "Schematic Design Of Pass Transistor Logic & Multiplexer" experiment,the back to experiments link is not present in the page

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Schematic%20Design%20Of%20Pass%20Transistor%20Logic%20%26%20Multiplexer/Schematic%20Design%20Of%20Pass%20Transistor%20Logic%20%26%20Multiplexer_35_Back%20to%20experiment_smk.org

Attachment:
41

QA_Schematic Design Of D-Latch and D-Flip Flop_Back to experiment_smk

Defect Description :
In the "Schematic Design Of D-Latch and D-Flip Flop" experiment,the back to experiments link is not present in the page instead the back to experiments link should be displayed on the screen inorder to view the list of experiments by the user

Actual Result :
In the "Schematic Design Of D-Latch and D-Flip Flop" experiment,the back to experiments link is not present in the page

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Schematic%20Design%20Of%20D-Latch%20and%20D-Flip%20Flop/Schematic%20Design%20Of%20D-Latch%20and%20D-Flip%20Flop_34_Back%20to%20experiment_smk.org

Attachment:
27

QA_Delay Estimation In Chain Of Inverters_Usability_smk

Defect Description :
In the home page/landing page of "Delay Estimation In Chain Of Inverters" experiment, an extra header link is present in the page where the extra header link should be removed as it is not required

Actual Result :
In the home page/landing page of "Delay Estimation In Chain Of Inverters" experiment, an extra header link is present in the page

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Delay%20Estimation%20In%20Chain%20Of%20Inverters/Delay%20Estimation%20In%20Chain%20Of%20Inverters_01_Usability_smk.org

Attachment:
39

QA_Design Of Digital Circuits Using Verilog_feedback_p1

Defect Description :
In the feedback page of "Design Of Digital Circuits Using Verilog" experiment,when we click on submit button with out entering the data in the corresponding fields an successul message is displayed on the screen instead an error message should be displayed on the screen as to enter the data in the corresponding fields

Actual Result :
In the feedback page of "Design Of Digital Circuits Using Verilog" experiment,when we click on submit button with out entering the data in the corresponding fields an successul message is displayed on the screen

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Design%20Of%20Digital%20Circuits%20Using%20Verilog/Design%20Of%20Digital%20Circuits%20Using%20Verilog_24_feedback_p1.org

Attachment:
10

QA_Layout Design_feedback_smk

Defect Description :
In the feedback page of "Layout Design" experiment,the cancel button is not present in the page instead the cancel button should be displayed on the screen as to unselect the selected radio buttons

Actual Result :
In the feedback page of "Layout Design" experiment,the cancel button is not present in the page

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Layout%20Design/Layout%20Design_22_feedback_smk.org

Attachment:
4

QA_Design Of D-Flip Flop Using Verilog_Back to experiments_smk

Defect Description :
In the "Design Of D-Flip Flop Using Verilog" experiment,the back to experiments link is not present in the page instead the back to experiments link should be displayed on the screen inorder to view the list of experiments by the user

Actual Result :
In the "Design Of D-Flip Flop Using Verilog" experiment,the back to experiments link is not present in the page

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Design%20Of%20D-Flip%20Flop%20Using%20Verilog/Design%20Of%20D-Flip%20Flop%20Using%20Verilog_29_Back%20to%20experiments_smk.org

Attachment:
14

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