virtual-labs/exp-latch-and-flip-flops-iiith

This experiment belongs to Digital Logic Design Full Name: Latch and Flip Flops

Introduction

Discipline	Fill your discipline name here
Lab	Fill your lab name here
Experiment	Fill your experiment name and number here

About the Experiment

Fill a brief description of this experiment here

Name of Developer	Fill the name of experiment owner here
Institute
Email id
Department

Contributors List

SrNo	Name	Faculty or Student	Department	Institute	Email id
1	.	.	.	.	.
2	.	.	.	.	.

exp-latch-and-flip-flops-iiith's Issues

ENHANCEMENT - Multiple Connections

1. Browser Environment Info:
   Google Chrome 113 on Linux(Ubuntu), Version 113.0.5672.92 (Official Build) (64-bit), X11 Window System.
   Browser Details
   User Agent: Mozilla/5.0 (X11; Linux x86_64) AppleWebKit/537.36 (KHTML, like Gecko) Chrome/113.0.0.0 Safari/537.36
2. Testing URL: https://virtual-labs.github.io/exp-latch-and-flip-flops-iiith

---

Type(s) of Issue

• Technical Issue
• Enhancement

Bug Screenshot

Description
If the connections are wrong/invalid, like connecting the outputs to two different connections, or connecting any of the ends to more than one connection, instead of allowing such connection, user experience would be enhanced if it did not allow multiple input sources to connect to the same endpoint.

BUGS - Incorrect/Unclear Instructions, Observations, Messages

1. Browser Environment Info:
   Google Chrome 113 on Linux(Ubuntu), Version 113.0.5672.92 (Official Build) (64-bit), X11 Window System.
   Browser Details
   User Agent: Mozilla/5.0 (X11; Linux x86_64) AppleWebKit/537.36 (KHTML, like Gecko) Chrome/113.0.0.0 Safari/537.36
2. Testing URL: https://virtual-labs.github.io/exp-alu-iiith/

---

1. Demo Section

• Restart Button Issue

Type(s) of Issue

• Incorrect Observations

Bug Screenshot

Description
After the simulation is completed in the demo section, the Observations Table on the right side displays the given message:
The issue here is that there is no such button called Restart in this section, so the user will not understand where to click to restart the simulation.

CORRECTION:

MODIFIED MESSAGE: Simulation has finished. Please click on Reset and repeat the instructions given to start again.

---

• Speed Issues

Type(s) of Issue

• Missing Instruction

Description
Whenever we pause the simulation, irrespective of the speed it had earlier, it always goes back to x1 speed when we pause and start back. We have to change the speed again to the desired values every time after pausing and restarting/ just starting. So, this could be mentioned in a more clear way by adding a new instruction as follows:

The default speed is reset to x1 automatically at the beginning of every simulation or whenever you pause and resume. If you want to change the speed, you can do so only while the simulation is running (only after starting or after resuming the simulation).

---

• Observation Section Paused Simulation message

Type(s) of Issue

• Unclear Message

Bug Screenshot

Issue
The message says the simulation stopped whenever we pause the simulation, but to make it clearer, it could say

Simulation has been Paused. Please click on the "Start" button to Resume.

---

Type(s) of Issue

• Spelling error

Bug Screenshot

Issue
It is not Invaid it must be Invalid

---

2 .Practice Section

• Selection of Bits & Confusion between Submit and Simulate

Type(s) of Issue

• Incomplete & Unclear Instructions

Bug Screenshot

Description
As seen in the picture above, in the (Practice) section, to simulate the circuit we built for different values of inputs, we must have the option to change the input values as per our convenience and verify. To do that, it is required to double-click on the input value bits to toggle them, but this feature is nowhere mentioned in the Instructions or anywhere else in the entire experiment additionally, in the demo section, we just had to single click to toggle the input bit value and so, the user will be confused as to how to give specific values to inputs.

Also, the instructions are unclear as to what simulate and submit buttons exactly do, as simulate option changes just the output bits which is not very evident for a first-time user. So, the instructions could be made more specific and clear as given below:
Instead of "Click on the "Simulate" button to simulate the circuit and see the output.", include these instructions:

• You can set the input bits, which are by default 1, to any values of your choice for testing, by double-clicking on them.
• Click on the "Simulate" button after setting the input bits as per your choice. This will simulate the circuit you built for the input bits set and will change the output bit values accordingly, for you to test your circuit.

Also, add these instructions at the end for a more clear understanding of what submit does.

• Clicking on "Submit" will display a "Success" or "Failure" message in the Observations Section according to the correctness of your circuit. It will also display a Truth Table verifying your circuit for different input values.

---

ENHANCEMENT - Finished Simulation Message in Practice Section

1. Browser Environment Info:
   Google Chrome 113 on Linux(Ubuntu), Version 113.0.5672.92 (Official Build) (64-bit), X11 Window System.
   Browser Details
   User Agent: Mozilla/5.0 (X11; Linux x86_64) AppleWebKit/537.36 (KHTML, like Gecko) Chrome/113.0.0.0 Safari/537.36
2. Testing URL: http://virtual-labs.github.io/exp-adder-latch-and-flip-flops-iiith

---

Type(s) of Issue

• Enhancement

Issue
When we click on simulate if there is no change in output bit value, it shows no change but in such cases, the user will not understand if the simulate button is working or not or he might doubt that has not clicked on the simulate button. So, we can make a message appear after the simulation as

Simulation has finished.

This message can disappear after a while.

ENHANCEMENT - Practice Section - T flip flop

1. Browser Environment Info:
   Google Chrome 113 on Linux(Ubuntu), Version 113.0.5672.92 (Official Build) (64-bit), X11 Window System.
   Browser Details
   User Agent: Mozilla/5.0 (X11; Linux x86_64) AppleWebKit/537.36 (KHTML, like Gecko) Chrome/113.0.0.0 Safari/537.36
2. Testing URL: http://virtual-labs.github.io/exp-latch-and-flip-flops-iiith

Type(s) of Issue

• Enhancement

Bug Screenshot

Description

• We see in the video that the T=0 gives 10 initially and as T=0 just gives us the previous value of QQ', we can say that QQ'=10 is the default value and we can let the users know that.

BUG - Practice -Section - Display Error message when disconnected

1. Browser Environment Info:
   Google Chrome 113 on Linux(Ubuntu), Version 113.0.5672.92 (Official Build) (64-bit), X11 Window System.
   Browser Details
   User Agent: Mozilla/5.0 (X11; Linux x86_64) AppleWebKit/537.36 (KHTML, like Gecko) Chrome/113.0.0.0 Safari/537.36
2. Testing URL: http://virtual-labs.github.io/exp-comparator-iiith

Type(s) of Issue

• Technical Issue

Bug Screenshot

Issue

• We see that when we do not connect Inputs to anything as seen in second screenshot, it will display error message. But if I have connected them earlier but later on deleted the connected components and then simulate/submit, it will not display error message and give results too.
• In the last Image too, R is not connected to anything. Originally it gives an error message but if I connect r to some gate and then later on I have deleted that gate,it will no more display error message when we simulate/submit even if theinput R of the RS Flip Flop is not connected to anything.Same thing happend=s with all the inputs and outputs of the RS Flip Flop.
• Similar issue occurs with all gates and all the input and output points of a JK Flip flop

---

BUG - Refreshing input output values after submit

1. Browser Environment Info:
   Google Chrome 113 on Linux(Ubuntu), Version 113.0.5672.92 (Official Build) (64-bit), X11 Window System.
   Browser Details
   User Agent: Mozilla/5.0 (X11; Linux x86_64) AppleWebKit/537.36 (KHTML, like Gecko) Chrome/113.0.0.0 Safari/537.36
2. Testing URL: http://virtual-labs.github.io/exp-latch-and-flip-flops-iiith

---

Type(s) of Issue

• Technical Error

Bug Screenshot

ISSUE
When we change the input bit values but instead of clicking on simulate, if we click on submit, and after that, we click on simulate, it will not consider the changes that have been done before the submit step and will give the output bit values that were there earlier only. And also, if you do not remember which inputs you have changed before the submit step and have not changed it back to what you want, then the output does not behave appropriately as it will show that we have changed the input bits but the output bits will not consider that change and it will get messier. This can be seen in the screenshot where we changed the value of R to 1, then clicked on submit and then clicked on simulate, it does not consider these changes and still prints the output as 0 instead of 1. So, to prevent all this, if we can refresh all the input and output bit values to default every time we click on submit, it will be easier for users to understand the process.

ENHANCEMENT - Table Formatting - Practice Section

1. Browser Environment Info:
   Google Chrome 113 on Linux(Ubuntu), Version 113.0.5672.92 (Official Build) (64-bit), X11 Window System.
   Browser Details
   User Agent: Mozilla/5.0 (X11; Linux x86_64) AppleWebKit/537.36 (KHTML, like Gecko) Chrome/113.0.0.0 Safari/537.36
2. Testing URL: https://virtual-labs.github.io/exp-latch-and-flip-flops-iiith

---

1. Truth Table in Observations section of Practice Section

Type(s) of Issue

• Formatting Issue
• Enhancement

Bug Screenshot(s)

Issue
The first screenshot shows the Observations section when we click on submit, it says success/failure and the truth table that verifies our circuit for different input values. But when we change the circuit connections and then click on simulate to test new connections, the Success/Failure message disappears but the truth table is still present as shown in the second screenshot. Removing them will add a good enhancement.

---

---

BUG- Demo-Invalid Results

1. Browser Environment Info:
   Google Chrome 113 on Linux(Ubuntu), Version 113.0.5672.92 (Official Build) (64-bit), X11 Window System.
   Browser Details
   User Agent: Mozilla/5.0 (X11; Linux x86_64) AppleWebKit/537.36 (KHTML, like Gecko) Chrome/113.0.0.0 Safari/537.36
2. Testing URL: http://virtual-labs.github.io/exp-latch-and-flip-flops-iiith

---

Type(s) of Issue

• Technical Issue

Bug Screenshot

Description

• The output when JK=00 must be same as the initial, which means QQ'=01 but it is QQ'=10 and the same output for JK=11, so both JK=00 & JK=11 cannot have same outputs since the initial state is always same here. So, when JK=00 output must be QQ'=01.
• In the last but 2 figures, when JK=01 and when JK=10 output is QQ'=01 wheres as for JK=10, it must be QQ'=10.
• In the last figure, we see that when JK=11, the output of the first two 3-input NAND gates must be 0 and 1 because:
  Initially, given that QQ'=01.
  Output of first 3-input NAND gate = NAND( SET,CLOCK,Q') = NAND (1,1,1)= 0
  Output of second 3-input NAND gate = NAND( RESET,CLOCK,Q) = NAND (1,1,0)= 1
  But it shows both outputs as 0 which is wrong.
• Also, since clock is always 1, the input to the 3rd and 4th 2-input NAND gate is always not(clock) = 0 and hence its output is always 1 irrespective of SET and RESET bits because of which the final last two 2-input nand gates which give Q and Q' will always have one input as 1, and so the output they give will not depend on the SET and RESET values. So, to give correct result, the clock cannot always be 1. The clock must go to 0 when the bit balls reach the third and fourth 2-input and gates so that the input they get from thenot gate at that time is 1, and this is how a clock should function. JK flipflops give output in one clock cycle which has both 1 and 0 values of clock and not just 1. The master operates when clock is 1and slave operates when clock is 0.
  REFERENCES:
• https://learnabout-electronics.org/Digital/dig54.php
  
• https://www.electronics-tutorials.ws/sequential/seq_2.html
  

BUG - Practice Section - Output Bit not Showing Values

1. Browser Environment Info:
   Google Chrome 113 on Linux(Ubuntu), Version 113.0.5672.92 (Official Build) (64-bit), X11 Window System.
   Browser Details
   User Agent: Mozilla/5.0 (X11; Linux x86_64) AppleWebKit/537.36 (KHTML, like Gecko) Chrome/113.0.0.0 Safari/537.36
2. Testing URL: http://virtual-labs.github.io/exp-latch-and-flip-flops-iiith

Type(s) of Issue

• Technical Issue

Bug Screenshot

Description

• The output bits are only black despite the values shown as output in the submit truth table as shown, but those values are not shown in the QQ' bits and they are only black.
• Also, the circuit is correct but the truth table shows it as incorrect.

PROPOSED SOLUTION
The QQ' could show 10 or anything else in the beginning so that its easy for users to use it to test for sequential circuits and simulation problem might get corrected if we give output some default values

BUG- Practice Section - Component Display

1. Browser Environment Info:
   Google Chrome 113 on Linux(Ubuntu), Version 113.0.5672.92 (Official Build) (64-bit), X11 Window System.
   Browser Details
   User Agent: Mozilla/5.0 (X11; Linux x86_64) AppleWebKit/537.36 (KHTML, like Gecko) Chrome/113.0.0.0 Safari/537.36
2. Testing URL: http://virtual-labs.github.io/exp-comparator-iiith

---

Type(s) of Issue

• Technical Issue

Bug Screenshot

Description
We see that the clock component is shown in the beginning when we just open practice section in the first figure but if we go to D flip-flop tab and come back to this, it shows an rs flip flop instead of a clock component in the end in the second figure. In the third figure we see, it shows a 3-input and gate if we go to D-Flipflop and come back. It shows a jk flip flop if we go to T flip flop and come back. So, it is showing the last component of the tab we opened just before opening the sr flip flop tab.

update

these bugs include :
adding reset button
resolving the click through issue from various components.
restricting the components from moving out of working area.
adding the delete option for the connectors.
editing a bit of css for easier experience.
reviewing the theory and demo part and changing accordingly.

ENHANCEMENT - Add contributors section

BUG - Demo section - Invalid Bit Colours in Animation

1. Browser Environment Info:
   Google Chrome 113 on Linux(Ubuntu), Version 113.0.5672.92 (Official Build) (64-bit), X11 Window System.
   Browser Details
   User Agent: Mozilla/5.0 (X11; Linux x86_64) AppleWebKit/537.36 (KHTML, like Gecko) Chrome/113.0.0.0 Safari/537.36
2. Testing URL: http://virtual-labs.github.io/exp-latch-and-flip-flops-iiith

Type(s) of Issue

• Technical Issue

Bug Screenshot

Description
After passing through NOT Gate, the yellow ball representing data must have become 1 i.e; blue butit remains yellow.

BUG - FORMATTING ERRORS

1. Browser Environment Info:
   Google Chrome 113 on Linux(Ubuntu), Version 113.0.5672.92 (Official Build) (64-bit), X11 Window System.
   Browser Details
   User Agent: Mozilla/5.0 (X11; Linux x86_64) AppleWebKit/537.36 (KHTML, like Gecko) Chrome/113.0.0.0 Safari/537.36
2. Testing URL: https://virtual-labs.github.io/exp-comparator-iiith

---

1. Theory Section

Type(s) of Issue

• Sentence Formation Issues
• Missing Image

Bug Screenshot

Description

• In the first image, 2d vectors is unnecessary there and should be removed.
• In the second image, it is written as Q and Q whereas it should be Q and Q'.Replace Q by Q' wherever required.
• In the third image, at is repeated twice.
• Modified Sentence: The following Digram Diagram depicts the change of JK flip flop Output with time pulse. It is negativve negative edge triggered.
• Image not available

---

2. Procedure Section

Type(s) of Issue

• Sentence Formation Issues

Bug Screenshot

• RS FLIP-FLOP
  
  
• Master-Slave JK Flip Flop
  
  
  
  

Description

MODIFIED STATEMENTS:

• RS FLIP-FLOP

  • The first NAND gate must be connected to S and second NAND gate to R as per the circuit diagram in the references provided below and also in the demo section.

  • REFERENCES:https://www.daenotes.com/electronics/digital-electronics/flip-flops-types-applications-woking
    

  • Drag the third NAND gate and connect its one of its input points to the output of the first NAND gate.

  • Drag the fourth NAND gate and connect its one of its input points to the output of the second NAND gate.

• Master-Slave JK Flip Flop
  • Drag the first 2-input NAND gate and connect its one of its input points to the output of the first 3-input NAND gate.
  • Drag the second 2-input NAND gate and connect its one of its input points to the output of the second 3-input NAND gate.
  • The output of fifth 2-input NAND gate connected to Q must be connected to the input of the second 3-input NAND gate and not the first. Similarly, output of the 6th 2-input NAND gate must be connected to the input of the first 3-input NAND gate and not the second. So,modified statements are:
    • Connect the output of the fifth 2-input NAND gate to the input point of the sixth 2-input NAND gate and also the input point of the second 3-input NAND gate.
    • Connect the output of the sixth 2-input NAND gate to the input point of the fifth 2-input NAND gate and also the input point of the first 3-input NAND gate.
  • Set the Values values of the J and K as you wish.
  • As per the truth table given in the Theory section for JK Flip flop shown in the next figure above, if JK=01, QQ'=01 and if JK=10, QQ'=10. So, the modified statement is:
    • If Clk is 1, the output bits Q and Q' are 1,0 and 0,1 when the J and K bits are 1,0 and 0,1 respectively.

---

3. Pretest Section

Type(s) of Issue

• Explanation Required

Bug Screenshot

QUESTION 4

QUESTION 5

Description

• QUESTION 4 EXPLANATION: OPTION d:
  • The "True" memory refers to the fact that the JK flip-flop can retain its state indefinitely until a specific input combination is applied
  • REFERENCE: [CHATGPT]

   The JK flip-flop does have a "True" memory.
The "True" memory refers to the fact that the JK flip-flop can retain its state indefinitely until a specific input combination is applied. This property allows it to function as a memory element in sequential logic circuits. By changing the inputs, the flip-flop can transition between different states and store information.
So, the correct answer is (d) True. The JK flip-flop has a True memory

• QUESTION 5 EXPLANATION: OPTION b:
  • A flip-flop is a bistable device because it has two stable states and can remain in either state until it is explicitly changed by an input signal.
  • REFERENCE: [CHATGPT]

The correct answer is (b) bistable. 

A flip-flop is a bistable device because it has two stable states and can remain in either state until it is explicitly changed by an input signal. The two stable states in a flip-flop are typically represented as logic 0 and logic 1, or more commonly as "reset" and "set" states. Flip-flops are widely used in digital circuits for storing and synchronizing data.

---

4. Demo Section

• JK FLIP-FLOP

** Types of Issues**

• Wrong Heading

Bug Screenshot

Description
Rename SET as J and RESET as K to avoid confusion.

4. Practice Section

• D Flip Flop

** Types of Issues**
-Spelling Errors

Bug SCreenshot

Description
The correct Spelling is Flip Flops. L must be small in Flops.

---