virtual-labs/exp-truth-table-gates-iitr

This experiment belongs to Digital Electronics IITR Lab.​​​​                                                 Full Name: "Verification and interpretation of truth table for AND, OR, NOT, NAND, NOR, Ex-OR, Ex-NOR gates"

Introduction (Round 0)

Discipline	Engineering
Lab	Digital Electronics
Experiment	1. Verification and interpretation of truth table for AND, OR, NOT, NAND. NOR, Ex-OR, Ex-NOR gates.

About the Experiment :

This experiment is to verify and interpret the logic and truth table for AND, OR, NOT, NAND, NOR, Ex-OR, Ex-NOR gates using RTL (Resistor Transistor Logic), DTL (Diode Transistor Logic) and TTL (Transistor Transistor Logic) logics in simulator 1 and verify the truth table for AND, OR, NOT, NAND, NOR, Ex-OR, Ex-NOR gates in simulator 2.

Name of Developer	R.S. Anand
Institute	IIT Roorkee
Email id	[email protected]
Department	Electrical Engineering

Contributors List

SrNo	Name	Faculty or Student	Department	Institute	Email id
1	R.S. Anand	Faculty	Electrical Engineering	IIT Roorkee, Roorkee	[email protected]
2	Jasbir Singh	Research Fellow	Electrical Engineering	IIT Roorkee, Roorkee	[email protected]
3	Rajeev Kumar	Research Fellow	Electrical Engineering	IIT Roorkee, Roorkee	[email protected]
4	Priyanshi Agarwal	Research Fellow	Electrical Engineering	IIT Roorkee, Roorkee	[email protected]