warclab/zycap

Zynq PR Management

zycap's Issues

Linux Image

Hello,
I'm trying to figure out if this system would still run on the current vivado systems.
Unfortunately the Image is no longer on the dropbox referred in the repo.
Any chance there is another way to reach it

Program hangs after PR

Hello,

I want to start with expressing my thankfulness for the tutorial file you prepared. Even though, there has been years apart and I am using a new version of Vivado (2017.3), I could easily follow the tutorial. However, at a point I stuck and would like to ask your guidance if possible.

When I follow the steps to run ZyCAP with Vivado using a baremetal test application, I receive the following dump on the UART console, but nothing more. It basically hangs there. Unfortunately, I -kind of- do not know what part to look it.

Reading data from register before PR
Register content is FCFCFCFC
Starting Reconfiguration
Reconfiguration speed: 1 MBytes/sec

Here I suspect of the bin files. The bif file example on the tutorial does not create two different bin files for the two bit files. Might it be an update in the bootgen? To overcome I created individual bif files for both modes, and created the bin files separately; however, I could not get the expected result at program's execution.

Moreover, I tried creating the bin files using Vivado's write_bitstream -bin_file. Weirdly, it creates the bin file which is not at the same size as the one bootgen created. There is 24 bytes difference in file sizes. With that bin file, the execution does not hang, it steps further; however, the new partial reconfiguration is not processed. I still get the same behaviour even though the reconfiguration returns with success. Here is the dump:

Reading data from register before PR
Register content is FCFCFCFC
Starting Reconfiguration
Reconfiguration speed: 1 MBytes/sec
Reading data from register after PR
Register content is FCFCFCFC

I would like to kindly as if you have any guidance to solve this issue?

Kind Regards,

Furkan