dmscnt and dmcmon disabled in Vivado based flows

[wfjm]

dmscnt and dmcmon disabled in Vivado based flows

[wfjm]

This synthesis issue is still in Vivado 2016.4. Due to other improvements timing closure is however reached for 80 MHz even with enabled dmcmon. The high place-and-route CPU time indicates however that this clock rate is at the edge and closure fragile.

To enable dmcmon change in sys_conf.vhd

constant sys_conf_dmscnt        : boolean := true;
constant sys_conf_dmcmon_awidth : integer := 9;

In case no timing closure is achieved for 80 MHz clock reduce the clock rate to 70 MHz by

constant sys_conf_clksys_vcomultiply : positive := 14;  -- vco  1400 MHz
constant sys_conf_clksys_outdivide : positive := 20;    -- sys   70 MHz

[wfjm]

At least mitigated with d14626c which allows to use dmcmon without the full state number generation logic in pdp11_sequencer. Reintroduced dmcmon in sys_w11a_n4 again. dmscnt is still deconfigured for vivado designs, but this has much less practical impact.

[wfjm]

Re-checked with Vivado 2022.1 for rtl/sys_gen/w11a/artys7_bram design,
Still "old" behavior, with sys_conf_dmscnt : boolean := true

• no INFO: [Synth 8-3354] encoded FSM ... using encoding 'one-hot' seen for pdp11_sequencer
• higher LUT/FLOP count in final design
• still timing closure, but with reduced WNS (0.112 vs 0.374)

This tool chain problem is still around. Label it wontfix.