Comments (1)
The Nexys4 (classic, with 16 MByte PSRAM) board on which most of the recent w11 was done broke in late July 2019 (see blog) and a Nexys A7 was ordered as replacement.
Basic tests with the test designs sys_tst_serloop2 and sys_tst_rlink_n4d and the BRAM-only w11 design sys_w11a_br_n4d worked fine.
But all tests involving the DDR2 memory interface failed. The culprit was quickly found, it was a mistake in the MIG configuration mig_a.prj, the polarity of the SYS_RST
signal was ACTIVE LOW
instead of ACTIVE HIGH
. After fixing this, the test designs sys_tst_mig_n4d and sys_tst_sram_n4d as well as the w11 implementation sys_w11a_n4d worked right away.
The tst_sram designs show nicely that the DDR2 on the Nexys A7 board is slightly slower than the DDR3 on the Arty A7 board
Board test time clock period UI_CLK
Nexys A7 37.36 s 3333 ps 75.0 MHz
Arty A7 35.77 s 3000 ps 83.3 MHz
The issue is closed with commit 563e230.
from w11.
Related Issues (20)
- CPU: several deficits in trap logic HOT 2
- CPU: src+dst deltas summed in mmr1 if register identical
- CPU: The AIB bit in MMU PDR register set independant of ACF field
- CPU: MMR0 trap bit set when access aborted
- CPU: no mmu trap when instruction which clears trap enable itself causes a trap HOT 1
- RK11: write protect action too slow
- migrate from Travis to GitHub actions HOT 2
- SimH scmd files fail on current 4.* version; only 3.* supported HOT 5
- time tbrun does not report correct CPU time
- asm-11 compiles nnn(pc) as nnn
- MMU: PDR A bit is set for every access
- MMU: ACF=1 traps on any access
- MMU: D space used instead of I space for PC deferred specifiers
- MMU trap delayed/lost when prefetch in s_idecode done HOT 1
- PSW changed after MMU aborts in dstw flows
- I have an ARTY S7 board, I'd like to try your w11 code. HOT 10
- add external ram support on basys3 Implementation HOT 3
- DZ11: modem control not implemented in backend
- DEUNA: buffer chaining not implemened in backend HOT 1
- A
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from w11.