wuxx/icesugar

iCESugar FPGA Board (base on iCE40UP5k)

iCESugar

中文 English

• iCESugar介绍
• 芯片规格
• 硬件说明
  • iCE40UP5K
  • iCELink
• 资源下载
• 开发环境搭建
• 视频教程
• FPGA教程
• 产品链接
• 参考

iCESugar介绍

iCESugar 是MuseLab基于Lattice iCE40UP5k设计的开源FPGA开发板，开发板小巧精致，资源丰富，板载RGB LED，Switch，TYPE-C-USB, Micro-USB，大部分IO以标准PMOD接口引出，可与标准PMOD外设进行对接，方便日常的开发使用。
板载的调试器iCELink经过精心设计，支持拖拽烧录，用户只需将综合出的FPGA bitstream文件拖拽至虚拟U盘中，即可实现烧录。iCELink亦支持虚拟串口以和FPGA进行通信，同时引出JTAG接口，方便用户对FPGA上实现的SoC进行调试。
Lattice的iCE40系列芯片在国外的开源创客社区中拥有大量拥趸，其所有的开发软件环境亦均为开源。一般来说，假若您使用Xilinx或者Altera系列的开发板，您需要安装复杂臃肿的IDE开发环境(而且一般为盗版，使用存在一定法律风险), 在未开始开发前，首先还先需要学会如何操作其复杂的IDE。 iCE40则使用完全开源的工具链进行开发，包括FPGA综合（yosys），布线（arachne-pnr & nextpnr）, 打包烧录（icestorm），编译（gcc），只需在Linux下输入数条命令，即可将整套工具链轻松安装，随后即可开始您的FPGA之旅，而且这一切都是开源的，您可仔细研究整个过程中任何一个细节的实现，非常适合个人研究学习，对于有丰富经验的开发者，亦可用来作为快速的逻辑验证平台。典型的基于iCE40系列的开源开发板有iCEBreaker、UPduino、BlackIce、iCEstick、TinyFPGA 等，社区中拥有丰富的demo可用于验证测试，或者作为自己开发学习的参考。
iCESugar是iCESugar系列的第一款开发板，iCESugar-nano(基于Lattice iCE40LP1k) 和 iCESugar-pro(基于Lattice ECP5)已经发布，以匹配不同的功能性能的需求。

芯片规格

iCE40UP5K-SG48

1. 5280 Logic Cells (4-LUT + Carry + FF)
2. 128 KBit Dual-Port Block RAM
3. 1 MBit (128 KB) Single-Port RAM
4. PLL, Two SPI and two I2C hard IPs
5. Two internal oscillators (10 kHz and 48 MHz)
6. 8 DSPs (16x16 multiply + 32 bit accumulate)
7. 3x 24mA drive and 3x hard PWM IP

硬件说明

iCE40UP5K

1. SPI Flash使用W25Q64（8MB）
2. 板载拨码开关和RGB LED可用于测试
3. 所有IO以标准PMOD接口引出，可用于开发调试

iCELink

iCESugar实现了一个板载的调试器iCELink，您可仅用一根USB线便可实现FPGA的烧录和调试，具体功能说明如下：

1. 拖拽烧录，将综合布线打包生成的bin文件（一般称之为配置或者逻辑）拖拽到iCELink的虚拟U盘中即可实现烧录
2. 虚拟串口，可用于和FPGA直接数据的发送接收
3. 支持JTAG, 可对FPGA上实现的SoC进行调试
4. 通过MCO输出12Mhz时钟，作为FPGA的外部时钟

虚拟机镜像

链接：https://pan.baidu.com/s/1qVSdwM7DnFbaS0xdqsPNrA
提取码：6gn3
user: ubuntu
passwd: ubuntu
所有环境包括综合(yosys)，布线(nextpnr)，打包(icesorm)，编译器(gcc) 已经预制好，启动即可开始使用。

开发环境搭建

推荐使用虚拟机镜像进行开发测试，简单方便。
FPGA工具链安装请参考icestorm
gcc工具链安装请参考 riscv-gnu-toolchain
也可直接下载xPack或者SiFive提供的预编译工具链

• https://xpack.github.io/riscv-none-embed-gcc/install/
• https://www.sifive.com/software

icesprog是为iCESugar开发的命令行烧写工具，仓库中已经提供，依赖libusb和hidapi，若自行搭建环境需要安装依赖的库
$sudo apt-get install libhidapi-dev
$sudo apt-get install libusb-1.0-0-dev

• Arch Linux 开发环境：AUR icesugar-git

# icesugar
yay -Syu icesugar

# icesugar-pro
yay -Syu icesugar-pro

# icesugar-nano
yay -Syu icesugar-nano

# icesugar-icesprog
yay -Syu icesugar-icesprog

视频教程

• 开源FPGA开发板-硬件介绍
• 开源FPGA开发板-开发环境搭建
• 开源FPGA开发板-RISC-V SoC烧录演示

FPGA教程

强烈推荐学习此教程，open-fpga-verilog-tutorial src/basic/open-fpga-verilog-tutorial目录中有对应的例程

产品链接

iCESugar FPGA Board

参考

RTL toolchain

http://www.clifford.at/icestorm/

Firmware toolchain

https://xpack.github.io/riscv-none-embed-gcc/install/ https://www.sifive.com/software

Examples

https://github.com/damdoy/ice40_ultraplus_examples
https://github.com/icebreaker-fpga/icebreaker-examples

SpinalHDL 教程

https://spinalhdl.github.io/SpinalDoc-RTD/SpinalHDL/Getting%20Started/index.html

开源FPGA单板iCESugar介绍

https://www.muselab-tech.com/wan-quan-shi-yong-kai-yuan-gong-ju-lian-de-fpgadan-ban/

icesugar's Issues

Is there a 'full pack' available including the ICESugar and several PMODs?

I'm looking into buying an ICESugar along with multiple PMOD peripherals. However, I didn't find any pack including more than a single PMOD.

ICESugar	29.54€	Pack	Alone
PMOD-VGA	36.30€	+6.76€	9.12€
PMOD-LED	33.76€	+4.22€	6.59€
PMOD-SWITCH	33.76€	+4.22€	6.59€
PMOD-AUDIO	35.45€	+5.91€	8.28€
PMOD-TFTLCD	37.98€	+8.44€	10.81€
PMOD-RGBLCD	-	-	19.25€ (8.27€ w/o screen)
		+29.55€	60.64€ (49.66€ w/o RGB screen)

Buying PMOD parts alone is ~2.36€ more expensive that buying one of them together with the board. I don't know whether that's an offer as a pack, or due to shipping.

The only option to get a "full pack" seems to be:

• (ICESugar + PMOD-LED) + PMOD-VGA + PMOD-SWITCH + PMOD-AUDIO + PMOD-TFTLCD + PMOD-RGBLCD = 87.81€
• or 76.83€ w/o RGB screen
• or 68.56€ w/o PMOD-RGBLCD
• or 77.00€ w/o PMOD-TFTLCD

Is that correct? Will everything be shipped together?

unable to run make prog

hi, my board is Lattice iCE40UP5k , when i plug it in, my ubuntu mount it as a drive and make prog not work, please help:

/home/peter/workspace/ice40_ultraplus_examples/leds>make prog
iceprog -S leds.bin
init..
Can't find iCE FTDI USB device (vendor_id 0x0403, device_id 0x6010 or 0x6014).
ABORT.
make: *** [Makefile:10: prog] Error 2

difference betwen icesprog and iceprog (from toolchain-ice40)

Hi

do you plan to publish the source code of icesprog ?

And can you explain what's the difference between icesprog and iceprog from https://github.com/YosysHQ/icestorm/tree/master/iceprog ?

Part number / datasheet for 0.96" LCD?

On the PMOD LCD 0.96" schematic the LCD is just listed as "TFTLCD_0.96_SPI".

Do you have a part number or datasheet for the LCD and LCD controller I can use to program for it?

1.5 schematic: Hard to see PMOD1 and UART are connected via J5

After some head-scratching, I realized the reason pin 4 seemed to be shorted high was that it's connected to STM32's UART TX via J5.

In the schematic, PMOD1 does clearly show how some of the pins are connected to the microusb port. However, it fails to show that some pins are also connected to J5.

It would be best if PMOD1's link with J5 was shown in the same manner as done with the USB pins.

What's the relation with OpenFPGA-ICE ?

Hi
https://github.com/OpenFPGA-ICE looks quite similar to your github,
and uses the same icesprog.

How the 2 boards are related ?

iceSugar v1.5 Clock @ 6MHz

I have just noticed that the ICE_CLK for my iceSugar v1.5 board is set at 6MHz. However the schematics indicate that the oscillator X1 is a 12MHz oscillator.

The only thing I can see that can divide the cock is the icelink.

I have tried with the iceprog tool as well to set the mco, but no luck.

$sudo ./icesprog -p
probe chip
board: [iCESugar]
flash: [w25q64] (8MB)
done

$ sudo ./icesprog -c 2
only iCESugar-Nano support mco select
^C

Can someone confirm this?

请增加tftlcd的例子

demo 中有一个MuraxSoC_pmod_tftlcd的例子，可以跑。但是没有源代码。
希望能提供lcd相关例子和代码。

make gateware failed

export PLATFORM=ice40_up5k_b_evn
export TARGET=base
export CPU=vexriscv
export CPU_VARIANT=linux
export FIRMWARE=linux

wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
chmod +x ./litex_setup.py
./litex_setup.py init install --user

./scripts/debian-setup.sh
./scripts/download-env.sh

source ./scripts/enter-env.sh
make gateware

#error

mkdir -p build/ice40_up5k_b_evn_base_vexriscv.linux/
time python -u ./make.py --platform=ice40_up5k_b_evn --target=base --cpu-type=vexriscv --iprange=192.168.100   --cpu-variant=linux --cpu-variant=linux  \
	2>&1 | tee -a /root/icesugar/icesugar/src/advanced/litex-buildenv/build/ice40_up5k_b_evn_base_vexriscv.linux//output.20210925-052953.log; (exit ${PIPESTATUS[0]})
Compat: SoCSDRAM is deprecated since 2020-03-24 and will soon no longer work, please update. Switch to SoCCore/add_sdram/soc_core_args instead...........thanks :)

Traceback (most recent call last):
  File "./make.py", line 169, in <module>
    main()
  File "./make.py", line 123, in main
    soc = get_soc(args, platform)
  File "./make.py", line 57, in get_soc
    soc = SoC(platform, ident=SoC.__name__, **soc_sdram_argdict(args), **dict(args.target_option))
  File "/root/icesugar/icesugar/src/advanced/litex-buildenv/targets/ice40_up5k_b_evn/base.py", line 105, in __init__
    type="cached+linker")
  File "/root/icesugar/icesugar/src/advanced/litex/litex/soc/integration/soc_core.py", line 252, in add_memory_region
    linker="linker" in type))
  File "/root/icesugar/icesugar/src/advanced/litex/litex/soc/integration/soc.py", line 166, in add_region
    raise
RuntimeError: No active exception to reraise

/////////////////////
run bootstrap.sh

ompiler_rt'...
fatal: \u7248\u672c\u5eab 'https://git.llvm.org/git/compiler-rt/' \u672a\u627e\u5230
fatal: \u7121\u6cd5\u8907\u88fd 'https://git.llvm.org/git/compiler-rt' \u5230\u5b50\u6a21\u7d44\u8def\u5f91 '/root/icesugar/icesugar/src/advanced/litex-buildenv/third_party/litex/litex/soc/software/compiler_rt'
\u8907\u88fd 'litex/soc/software/compiler_rt' \u5931\u6557\u3002\u5df2\u6392\u7a0b\u91cd\u8a66\u4f5c\u696d
\u6b63\u8907\u88fd\u5230 '/root/icesugar/icesugar/src/advanced/litex-buildenv/third_party/litex/litex/soc/software/compiler_rt'...
fatal: \u7248\u672c\u5eab 'https://git.llvm.org/git/compiler-rt/' \u672a\u627e\u5230
fatal: \u7121\u6cd5\u8907\u88fd 'https://git.llvm.org/git/compiler-rt' \u5230\u5b50\u6a21\u7d44\u8def\u5f91 '/root/icesugar/icesugar/src/advanced/litex-buildenv/third_party/litex/litex/soc/software/compiler_rt'
\u7b2c\u4e8c\u6b21\u5617\u8a66\u8907\u88fd 'litex/soc/software/compiler_rt' \u5931\u6557\uff0c\u4e2d\u6b62\u4f5c\u696d
fatal: \u7121\u6cd5\u905e\u8ff4\u9032\u5b50\u6a21\u7d44\u8def\u5f91 'third_party/litex'
////////////////////
by the way way can ice40_up5k_b_evn success run simple linux or zepyhr?

how to build from soc to app

I want to build soc and os firmware finally is riscv gcc compile a app test
Now I done toplevel.bin of Murax

then how to do?
go to build https://github.com/wuxx/litex-buildenv ?

你好 可以推荐几个相关的开源社区网址吗？

可以推荐几个相关的开源社区网址吗？

Is this board compatible to the Lattice Diamond?

Hi,

Is this board compatible to the Lattice Diamond?

Most of your tutorial are based on open source tools, I wonder if this board can work with Lattice Diamond.

Thanks

compiler-rt download failed and fixed

gedit $HOME/icesugar/icesugar/src/advanced/litex-buildenv/third_party/litex/.gitmodules
url = https://git.llvm.org/git/compiler-rt
#change to
url = https://github.com/llvm-mirror/compiler-rt.git

could I substutite picorv32/scripts/icestorm .v and .pcf

https://github.com/wuxx/icesugar/blob/master/src/advanced/picorv32/scripts/icestorm
I wan to substutite example.v example.pcf
to
picorv32/picosoc/icesugar.v picorv32/picosoc/icesugar.pcf
can run it well?

and If I using Murax of VexRiscv how to do? burn the Murax bin then burn the firmware bin
or I need what tool combine them

The board is not working that keeps showing a "Fail.TXT"

Hi, I just receive the board and try to use the demonstration bin file.

But every time I drag the bin file to the ICELINK in file explorer.

The board doesn't read the bin file, but showing a "FAIL.txt" file, which indicates the following lines:

error: The transfer timed out.
type: transient, user

What am I suppose to do?

uart_echo unable to compile

hi

/home/peter/workspace/icesugar/src/basic/verilog/uart_echo>make
Makefile:5: iCELink path: /media/peter/iCELink
yosys -p "synth_ice40 -blif pll_uart_mirror.blif" pll_uart_mirror.v

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <[email protected]>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.30+48 (git sha1 14d50a176, clang 14.0.0-1ubuntu1 -fPIC -Os)


-- Parsing `pll_uart_mirror.v' using frontend ` -vlog2k' --

1. Executing Verilog-2005 frontend: pll_uart_mirror.v
Parsing Verilog input from `pll_uart_mirror.v' to AST representation.
pll_uart_mirror.v:69: ERROR: syntax error, unexpected TOK_REG
make: *** [Makefile:8: build] Error 1

thanks

Directly configuring iCE40 in slave mode.

The "||" (prog iCE) jumper configuration allows the iCElink to configure the iCE40 in slave mode but there's no such option in icesprog. How would I go about having the iCElink directly configure the iCE40?

As a side note, the way the schematic names the busses is a bit confusing, I think ICE_MISO should really be called ICE_SO since it can operate in master and slave mode, same with ICE_MOSI (-> ICE_SI) this would make the schematic a lot clearer especially when in the default configuration (with the jumpers in "=" mode) ICE_MISO actually acts as ICE_MOSI and vice versa (the iCE40 is the bus master during the configuration).

Source code for ICELink

Is the source code for ICELink open?
I can find it anywhere.
If not, is it a "not yet", or no plans on open sourcing it?
It is a great tool, but I'm having some weird intermittent problems after dragging in a new program.

could I use Murax of VexRiscv + picorv32 firmware

1. iceprog toplevel.bin in Murax of VexRiscv (gateware)
2. iceprog firmware.bin in picorv32
   can do them both?

burn the gateware then firmware
then I can add instruction in Murax and modify riscv gcc compiler
then modify the firmware to test new instruction

could I use icesugar impelement VexRiscv

in https://github.com/wuxx/VexRiscv
VexRiscv small and productive (RV32I, 0.82 DMIPS/Mhz) ->
Artix 7 -> 232 Mhz 816 LUT 534 FF
Cyclone V -> 155 Mhz 492 ALMs
Cyclone IV -> 155 Mhz 1,111 LUT 530 FF
iCE40 -> 63 Mhz 1596 LC

can icesugar impelement VexRiscv?

iCELink not found

When i try to "make prog_flash" it cannot find the path... look like iceLink removed from the repro?

virtual-machine-image not in mega.nz,

virtual-machine-image link in mega.nz is death, and using baidu, only for local Chinese users in Chinese language. Is there another source of virtual machine image? Thanks in advance

Can this board run RISC-V

Hi
Can this board run RISC-V? Enough resources?
thanks

Tag for packagers

Please, add some git tag to the repo, which packagers can use for building a version string using git describe.

Demo: uart_tx not working

I tried both the prebuilt binary and to rebuild it myself - no output on the usb-c serial:

@cdone:1
@reset
@cdone:0
@prog [0x00000000]
@prog [0x00010000]
@start
@cdone:1

and if i connect the micro usb to my pc, no new serial devices appear (i'm using Linux, so no /dev/ttyUSB* show up) so i can't connect there.

How is one supposed to run this demo?

UART access

Hello. I am trying to use the RX and TX pins to communicate the computer with the FPGA but I see that pins are connected to iCElink UART3 and I'm not sure you can communicate with that UART through the USB-C or how to do it. Thank you.

Mix of arachne and nextpnr Makefile's

The basic verilog examples in src/basic/verilog use a mix of arachnepnr and nextpnr, but I believe they should all use nextpnr as arachnepnr is no longer maintained.

The README shows the need for "arachne-pnr & nextpnr", couldn't this be reduced to just nextpnr if all the Makefile's are converted to use nextpnr?

Would it be helpful to create a pull request with all the Makefile's using nextpnr?

Drag&Drop fail with multi-image.

When you use a packet bitstream generated with icemulti and use a Drag&Drop iCELink feature, always fail with a time out error.

$ icemulti -v -p0 pwm.bin picorv32.bin leds.bin pll.bin -o icemulti_test.bin
Place image 0 at 0000a0 .. 01973a (`pwm.bin')
Place image 1 at 01973a .. 11b176 (`picorv32.bin')
Place image 2 at 11b176 .. 134810 (`leds.bin')
Place image 3 at 134810 .. 14deaa (`pll.bin')

Drag&Drop file icemulti_test.bin and get this FAIL file:

Can Icesugar support this mod - ledpanel ??

Hi,

Can this pmod be supported by icesugar ?

https://github.com/icebreaker-fpga/icebreaker-pmod/tree/master/led-panel/v1.2c

Thanks

Support for Lattice downloader environment

It would be greate if the board could support the Lattice environment in a newer version.

What I'd like to propose is the following.
The board should include a header where the iCE40 SPI pins and the CRESET_B pin are routed out.

Or just the CRESET_B,ICE_SS,ICE_SCK should need a header because the ICE_MOSI and ICE_MISO are already routed out to J3

share build Murax of VexRiscv on IntelliJ IDEA

http://fatalfeel.blogspot.com/2021/09/risc-v-on-icesugar.html

ICELINK open Fail on MAC M1 with ICESUGAR

Hello,

Currently using the Icesugar on MAC M1, is there any support for it ? I initially thought yes since the iceprog and icesprog are supported under rosetta. Anyway seems the problem might only be the Debugger ?

thanks for the Help

icesprog fail on windows.

icesugar/tools/src/icesprog.c

Line 659 in 6424e0d

if (read(fd, flash_buf, st.st_size) != st.st_size) {

On windows it fails there. Windows needs a flag O_BINARY when using binary files with open(). Otherwise newline sequences accidentally found in the binary stream are converted by mistake so this check that should be redundant actually fails. In the file maybe there is 0x10,0x13 and it reads 0x13 only, so it appears to read less bytes.

Flash reading from the iCE40 UltraPlus

I'm trying to communicate with built-in SPI flash but it does not respond to any commands - I tried the sources of flash example and JEDEC ID request. Looks like flash chip (Winbond 25Q64JVSIQ) is different from what is used in the example.

Don't forget to put the breakout board in flash mode using the jumpers on J6!

this is unclear too - how it relates to icesugar... When I set the jumpers vertically, the board does not load bitstream.

Maybe there is no way to address built-in SPI flash programmatically?

What use really has the jumper J1?

Pin 35 from FPGA is an output from internal PLL (ICE_CLK), so is an input on microcontroller STM32 (as a clock?).
Why need a jumper here? What is it used for?

Is there a datasheet for the 2.8inch lcd screen?

Is there a datasheet for the smaller 2.8inch lcd screen (https://www.aliexpress.com/item/1005001505396954.html)?

icesprog is available in official MSYS2 repositories

During the last weeks, some PRs were proposed with regard to building and packaging icesprog (#16, #17, #18, #19).
I'm glad to tell that icesprog is now available in official MSYS2 repositories:

• https://github.com/msys2/MINGW-packages/tree/master/mingw-w64-icesprog
• https://packages.msys2.org/package/mingw-w64-i686-icesprog
• https://packages.msys2.org/package/mingw-w64-x86_64-icesprog

Therefore, users on Windows can install icesprog through pacman -S mingw-w64-x86_64-icesprog (64 bits) or pacman -S mingw-w64-i686-icesprog (32 bits); and they are ready to go!

user@DESKTOP MINGW64 /d/icesugar/demo
$ icesprog -w leds.bin
flash offset: 0x00000000
write flash (104090 (0x1969a) Bytes)
write 0x00000000
write 0x00010000
done

/cc @juanmard

any plan to support icestudio and apio?

It's' a visual editor for open FPGA boards, at https://github.com/FPGAwars/icestudio (sample config for boards: https://github.com/FPGAwars/icestudio/tree/develop/app/resources/boards, need to create a folder and 3 config files, and generates pinout.json from pinout.pcf (I'm assuming src/common/io.pcf is the proper pinout ) )

it relies on apio, a wrapper of other tools (
https://apiodoc.readthedocs.io/en/stable/source/contribute/support_new_board.html explains how to add a board to apio

RGBLCD

Hey,

I have the larger PMOD LCD from the aliexpress store. Looking at the src folder, the only example I can find is the rgblcd one. However this does not work (pcf unconstrained errors).

I noticed the pin labels on the lcd board looks like it is using SPI (MOSI etc), while the PCF file in the example references Hsync, Vsync and pins for the different RGB colours, however the pin numbers do not all align with the 2 PMODS). Am I right in thinking this example is not meant for the muselab TFT LCD PMOD board?

If not, is there anywhere I can find examples or documentation to get started?

Submodule fetch failure

$ git fetch -a --recurse-submodules
Fetching submodule src/advanced/VexRiscv
Fetching submodule src/advanced/VexRiscv/src/test/resources/VexRiscvRegressionData
Fetching submodule src/advanced/iceZ0mb1e
Fetching submodule src/advanced/litex-buildenv
Fetching submodule src/advanced/litex-buildenv/third_party/edid-decode
Fetching submodule src/advanced/litex-buildenv/third_party/flash_proxies
Fetching submodule src/advanced/litex-buildenv/third_party/litedram
Fetching submodule src/advanced/litex-buildenv/third_party/liteeth
Fetching submodule src/advanced/litex-buildenv/third_party/litepcie
Fetching submodule src/advanced/litex-buildenv/third_party/litesata
Fetching submodule src/advanced/litex-buildenv/third_party/litescope
Fetching submodule src/advanced/litex-buildenv/third_party/liteusb
Fetching submodule src/advanced/litex-buildenv/third_party/litevideo
Fetching submodule src/advanced/litex-buildenv/third_party/litex
Fetching submodule src/advanced/litex-buildenv/third_party/litex/litex/build/sim/core/modules/ethernet/tapcfg
Fetching submodule src/advanced/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule
Fetching submodule src/advanced/litex-buildenv/third_party/litex/litex/soc/cores/cpu/minerva/verilog
Fetching submodule src/advanced/litex-buildenv/third_party/litex/litex/soc/cores/cpu/mor1kx/verilog
Fetching submodule src/advanced/litex-buildenv/third_party/litex/litex/soc/cores/cpu/picorv32/verilog
Fetching submodule src/advanced/litex-buildenv/third_party/litex/litex/soc/cores/cpu/rocket/verilog
Fetching submodule src/advanced/litex-buildenv/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog
Could not access submodule 'litex/soc/software/compiler_rt'
Fetching submodule src/advanced/litex-buildenv/third_party/litex-renode
Fetching submodule src/advanced/litex-buildenv/third_party/migen
Fetching submodule src/advanced/litex-buildenv/third_party/nmigen
Errors during submodule fetch:
        third_party/litex
Fetching submodule src/advanced/up5k-demos
Fetching submodule src/advanced/up5k_6502
Fetching submodule src/advanced/up5k_6502/osdvu
Fetching submodule src/advanced/up5k_6502/verilog-6502
Fetching submodule src/advanced/usb
Errors during submodule fetch:
        src/advanced/litex-buildenv

What is the purpose of J7?

Comparing the schematics of v1.4 and v1.5, I found the difference to be the addition of J7, which seems to duplicate 4 of the pins in PMOD1:

The render and photo of v1.0 and v1.3, respectively, show that J7 was not there before. Comparing to a photo of v1.5 it looks like the distance between PMOD2 and PMOD3 was increased.

My understanding is that J7 was added for PMOD-RGBLCD, which has 30 pins (2x15). Hence a female angled 2x3P connector such as the following needs to be soldered in J7 for using PMOD-RGBLCD:

I assume that the spacing between PMOD connectors in PMOD-VGA and PMOD-TFTLCD matches the "new" separation in the v1.5 board design, and not the previous. With regard to the PMOD specification it seems that v1.5 complies with the separation between PMODs (22.86mm or 0.90"). Therefore, "standard" peripherals with two PMODs can be connected to the ICESugar now. Say, Pmod SSD or Pmod motor driver. By the same token, the PMOD-VGA and PMOD-TFTLCD of Muse Lab Factory Store can be used with any other board providing two properly spaced PMODs. Is this correct?

Question: Is there a USB PHY for the microUSB?

Hi, and thanks for an awesome project. I have purchased an IceSugar FPGA board but have a question about the microUSB port. From inspecting the schematics it seems as if the D+ an D- pins are directly connected to IOB_18A and IOB_16A on the Lattice ICE40. I am not experienced in this domain, but I would have expected a USB PHY chip to be connected to the microUSB connector and a serial RX/TX interface of the USB PHY connected to the FPGA.

Am I missing something here?

Again, thanks for a cool project, I am looking forward to using your board.

• Erling

Get or set data from SPI flash.

How do I get or set arbitrary binary data to the SPI flash through the iCELink (either drag and drop or icesprog)?

icesprog iCELink open fail

I have an iCESugar-nano board with v1.1a iCELink firmware. Provided icesprog binary isn't the latest one: it doesn't have clock select and gpio control features. Device programming works fine, but I also need these features.

I built both v1.1a and v1.1b icesprog binaries from sources, however, when I try to program the device, I get an output: iCELink open fail!

TFTLCD - SPI Register map

Hi,
Where can I find datasheet with SPI register Map for pmod_tftlcd-v1.1?
From documentation, LCD driver IC is NV3047, but I can't find any information on that part.
Thanks.

advanced build feature request for IntelliJ IDEA

could add sbt build for IntelliJ IDEA

https://github.com/wuxx/icesugar/tree/master/src/advanced

hope here can add chisel3 build for for IntelliJ IDEA