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onnx2c

Open Neural Network Exchange to C compiler.

onnxruntime

ONNX Runtime: cross-platform, high performance scoring engine for ML models

open-dla-performance-profiler

Performance profiling for neural network, deep learning and machine learning models on different open DLA architectures

open-dnn

open-source-fpga-resource

A list of resources related to the open-source FPGA projects

opentpu

A open source reimplementation of Google's Tensor Processing Unit (TPU).

openwifi

open-source 802.11 WiFi baseband chip/FPGA design

or1ksim

The OpenRISC 1000 architectural simulator

oram_fpga

FPGA related files for ORAM

orb_fpga

orb_slam3

ORB-SLAM3: An Accurate Open-Source Library for Visual, Visual-Inertial and Multi-Map SLAM

osdi21_ae

Artifact for OSDI'21 GNNAdvisor

paradnn

ParaDnn: A systematic performance analysis methodology for deep learning.

pareto

Pareto Frontier Computation

pasc

Parallel Array of Simple Cores. Multicore processor.

persian-noc

A synthesizable VHDL based cycle accurate PERformance SImulation Architecture for Networks-on-chip. PERSIAN-NoC is a parameterized RTL model for evaluating the performance factors of NoC based interconnection networks.

pet

PET: Optimizing Tensor Programs with Partially Equivalent Transformations and Automated Corrections

petalinux

Repository used to support automated builds under PetaLinux tools that use Yocto.

pillars

An integrated CGRA design framework

pimsim

PIMSim is a Process-In-Memory Simulator with the compatibility of GEM5 full-system simulation.

pincachesim

Cache Simulation Using PIN

pipeswitch

PipeSwitch: Fast Pipelined Context Switching for Deep Learning Applications

planaria.code

pp4fpgas-cn

中文版 Parallel Programming for FPGAs

prim-benchmarks

PrIM (Processing-In-Memory benchmarks) is the first benchmark suite for a real-world processing-in-memory (PIM) architecture. PrIM is developed to evaluate, analyze, and characterize the first publicly-available real-world PIM architecture, the UPMEM PIM architecture. Described by Gómez-Luna et al. (preliminary version at https://arxiv.org/abs/2105.03814).

proxylessnas

[ICLR 2019] ProxylessNAS: Direct Neural Architecture Search on Target Task and Hardware.

pspin

PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing

public

puma-simulator

PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and runs ML models compiled using the puma compiler.

pwc

Papers with code. Sorted by stars. Updated weekly.