wzcboy / mycpu Goto Github PK

make a simple mips CPU

Verilog 13.19% SystemVerilog 0.22% VHDL 78.59% V 0.86% Assembly 6.85% Makefile 0.01% C 0.16% Pascal 0.01% HTML 0.01% Shell 0.07% Stata 0.01% Forth 0.01% Tcl 0.01% JavaScript 0.02% Batchfile 0.01% C++ 0.02%

mycpu's Introduction

这是一个小学期的MIPS CPU项目
1.采用五级流水线
2.实现了写回策略的cache
3.除法器使用《自己动手写CPU》中除法器
4.接上了龙芯提供的axi转换桥
5.通过89个功能测试，性能测试和下板验证
代码有参考吕昱峰学长和袁福焱学长，感谢！

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