Project of the VLSI course in our 3rd year in the Faculty of Engineering, Cairo University. Mainly consists of three mini projects which are: adders mania, multipliers maina, and generating the chip.
The adders are the building blocks of all “compute” units. Their performance impacts the whole chip. so in this mini project, we:
- Designed and implemented using Verilog the following 32-bit signed adders
- Verilog (‘+’) version of adders
- Ripple Carry Adder
- Carry Look-Ahead Adder
- Carry Bypass Adder
- Carry Select Adder
- Floating Point Adder (IEEE-standard) using Verilog (‘+’) version of adders
- Implemented a testbench to test the above adders: Covering 8 cases:
- Overflow of positive numbers.
- Overflow of negative numbers.
- Addition of positive and negative number
- Addition of positive and positive number
- Addition of negative and negative number
- Additional 3 random test cases
- Synthesis of the adders.
- Apply post-synthesis simulation using our previously made testbench.
For more details, see Adders Mania Presentation
The multiplier is another important block in the chip. So in this mini project, we:
- Designed and implemented using Verilog the following 32-bit signed multipliers
- Verilog (‘*’) version of multiplier
- Multiplier Tree (combinational)
- Sequential Multiplier using shift & accumulate
- Booth Algorithm
- Floating Point Multiplier (IEEE-standard) using Verilog (‘*’) version of multiplier
- Implemented a testbench to test the above multipliers: Covering 8 cases:
- Multiplication of positive and negative number.
- Multiplication of positive and positive number.
- Multiplication of negative and negative number.
- Multiplication of negative and positive number.
- Multiplication by zero.
- Multiplication by 1.
- Additional 2 random test cases.
- Synthesis of the multipliers.
- Apply post-synthesis simulation using our previously made testbench.
For more details, see Multipliers Mania Presentation
After synthesizing both floating point adder and multiplier, we generated the chip by placing and routing the adder and multiplier with similar constraints to synthesis. After this step we:
- Applied post-routing simulation using our previously made testbench with including our sdf files
- Generated the final GDS file for each design.
For each adder and multiplier we generated post-synthesis reports of:
- Total Area
- Max Delay
- Max Slack
- Min Slack
- Total Power
- clk
Which can be found in Adders-Mania/Output folder and Multipliers-Mania/Output folder
For the floating point adder and multiplier we generated post-routing reports and GDS files which can be found in Routing folder
Ahmed Samy |
Kareem Samy |
Nancy Ayman |
Yara Hisham |
This software is licensed under MIT License, See License
React
Typescript
Django
Laravel
Facebook
Microsoft
Google
Alibaba
D3
Tencent