yarahisham61/pipelined_processor

Piplined_Processor

Table of Contents

• Overview
• Design
• ISA
• Control Signals
• Contributors
• License

Overview

The processor in this project has a RISC-like instruction set architecture. There are eight 4-byte general purpose registers; R0, to R7. Another two specific registers, One works as a program counter (PC). The other works as a stack pointer (SP); and hence; points to the top of the stack. The initial value of SP is (2^12-1). The memory address space is 4 KB of 16-bit width and is word addressable. ( N.B. word = 2 bytes). The data bus between memory and the processor is 16-bit widths for instruction memory and 32-bit widths for data memory.

When an interrupt occurs, the processor finishes the currently fetched instructions (instructions that have already entered the pipeline), then the address of the next instruction (in PC) is saved on top of the stack, and the PC is loaded from address [2-3] of the memory (the address takes two words). To return from an interrupt, an RTI instruction loads the PC from the top of the stack, and the flow of the program resumes from the instruction after the interrupted instruction.

Design

ISA

• Zero operand instructions

  Instruction	Opcode
  NOP	000-0000
  RET	000-1000
  RLT –flag restore	000-1001

• One register instructions

  Instruction	Opcode
  NOT	001-0000
  INC	001-0001
  DEC	001-0010
  NEG	001-0011
  OUT	001-0100
  IN	001-0101
  POP	001-0110
  PUSH	001-0111
  PROTECT	001-1011
  FREE	001-1010
  JZ	001-1100
  CALL	001-1110
  JMP	001-1101

• Two registers instructions

  Instruction	Opcode
  SWAP	010-1111
  CMP	010-1110

• Three registers instructions

  Instruction	Opcode
  ADD	011-0001
  SUB	011-0010
  AND	011-0011
  OR	011-0100
  XOR	011-0101

• Two registers and immediate instruction

  Instruction	Opcode
  ADDI	110-0000

• One registers and immediate instruction

  Instruction	Opcode
  BITSET	101-0000
  LDM	101-1111
  RCL	101-1101
  RCR	101-1100
  LDD	101-1110
  STD	101-0001

Control Signals

Instruction	mem_read	immediate_value	branch	mem_write	reg_write1	reg_write2	reg_read1	reg_read2	reg_read3	stack_read	stack_write	protectAfree	protectOfree	inOout	inAout	alu_op
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0000
NOT Rdst	0	0	0	0	1	0	1	0	0	0	0	0	0	0	0	0001
NEG Rdst	0	0	0	0	1	0	1	0	0	0	0	0	0	0	0	0010
INC Rdst	0	0	0	0	1	0	1	0	0	0	0	0	0	0	0	0011
DEC Rdst	0	0	0	0	1	0	1	0	0	0	0	0	0	0	0	0100
OUT Rdst	0	0	0	0	0	0	0	0	0	0	0	0	1	1	0000	0
IN Rdst	0	0	0	0	1	0	0	0	0	0	1	0	1	0	0000	0
SWAP Rsrc, Rdst	0	0	0	0	1	1	1	1	0	0	0	0	0	0	0101	0
ADD Rdst, Rsrc1, Rsrc2	0	0	0	0	1	0	1	1	1	0	0	0	0	0	0110	0
ADDI Rdst, Rsrc1, Imm	0	1	0	0	1	0	1	1	0	0	0	0	0	0	0110	0
SUB Rdst, Rsrc1, Rsrc2	0	0	0	0	1	0	1	1	1	0	0	0	0	0	0111	0
AND Rdst, Rsrc1, Rsrc2	0	0	0	0	1	0	1	1	1	0	0	0	0	0	1000	0
OR Rdst, Rsrc1, Rsrc2	0	0	0	0	1	0	1	1	1	0	0	0	0	0	1001	0
XOR Rdst, Rsrc1, Rsrc2	0	0	0	0	1	0	1	1	1	0	0	0	0	0	1010	0
CMP Rsrc1, Rsrc2	0	0	0	0	0	0	1	0	0	0	0	0	0	0	1011	0
BITSET Rdst, Imm	0	1	0	0	1	0	1	0	0	0	0	0	0	0	1100	0
RCL Rsrc, Imm	0	1	0	0	1	0	1	0	0	0	0	0	0	0	1101	0
RCR Rsrc, Imm	0	1	0	0	1	0	1	0	0	0	0	0	0	0	1110	0
PUSH Rdst	0	0	0	1	0	0	1	0	0	1	0	0	0	0

Contributors

Ahmed Samy

Kareem Samy

Nancy Ayman

Yara Hisham

License

This software is licensed under MIT License, See License