- Clear Board Parameters
- Data Rate 1G
- Standard SGMII
- Core Functiionality ** LVDS Serial ** Ref Clk 625MHz
- Management Options ** NO MDIO ** Yes Auto Negotiation
- NO SGMII PHY Mode
- Include Shared Logic in Core
- Clear Board Parameters
- Data Rate 1G
- Interface ** PHY Interface: internal ** MAC Speed: 1000Mbps ** internal mode clock source: user clk2 ** Management Type: AXI4-Lite, Frequency 125.00MHz ** YES MDIO and IO Buffers
- Features ** Check Statistics (64-bit) and Statistics Reset only
Make sure there are following lines in config/project.tcl:
# Create project
create_project top ./ # possibly with -part xcku040-ffva1156-2-e
then
mkdir top; cd top/
vivado -mode tcl -source ../config/project.tcl
# open GUI
start_gui
# start synthesis
launch_runs synth_1 -jobs 8
# start implementation
launch_runs -jobs 8 impl_1 -to_step write_bitstream
# or do everything in tcl terminal
open_project /path/to/example.xpr
launch_runs -jobs 8 impl_1 -to_step write_bitstream
wait_on_run impl_1
exit
project.tcl
is generated via File->Write Project Tcl with everything unchecked.