yunjiaxi/cs145-computer-architecture-experiments

Use Vivado to implement MIPS single-cycle and pipeline processor

CS145-Computer-Architecture-Experiments

Use Vivado to implement MIPS single-cycle and pipeline processor

• Lab 1

  Simple practice

• Lab 2

  1 bit & 4 bit Adder

• Lab 3

  MIPS processor componments -- Controller & ALU

• Lab 4

  MIPS processor componments -- Register & Memory

• Lab 5

  MIPS single-cycle processor

  Support 16 MIPS instructions(add, sub, and, or, addi, andi, ori, slt,lw, sw, beq, j, jal, jr, sll, srl)

• Lab 6

  MIPS pipeline processor

  Support Stall, Forwarding

  Support 16 MIPS instructions(add, sub, and, or, addi, andi, ori, slt,lw, sw, beq, j, jal, jr, sll, srl)