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psp

pspin

PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing

pyexcel

Single API for reading, manipulating and writing data in csv, ods, xls, xlsx and xlsm files

pythonplantsvszombies

a simple PlantsVsZombies game

pythonsupermario

SuperMarioBros game written by python (support level 1-1 to level 1-4)

pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL

qemu-hdl-cosim

VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs

reapr

REAPR (Reconfigurable Engine for Automata Processing) is a general-purpose framework for accelerating automata processing applications such as regular expressions. REAPR is currently only compatible with SDAccel-capable Xilinx FPGA boards.

regex-fpga

Accelerating the regular expression matching on FPGA for applications in Networking and Bioinformatics.

regulair

Regex library for FPGAs

riscv-boom

SonicBOOM: The Berkeley Out-of-Order Machine

robustvideomatting

Robust Video Matting in PyTorch, TensorFlow, TensorFlow.js, ONNX, CoreML!

sc-fegan

SC-FEGAN : Face Editing Generative Adversarial Network with User's Sketch and Color

simbus

Icarus SIMBUS

skywater-pdk

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

spinalhdl

Scala based HDL

stanford-cs-229-cn

A Chinese Translation of Stanford CS229 notes 斯坦福机器学习CS229课程讲义的中文翻译

sv-parser

SystemVerilog parser library fully complient with IEEE 1800-2017

systemverilog-python

Systemverilog DPI-C call Python function

ugatit

Official Tensorflow implementation of U-GAT-IT: Unsupervised Generative Attentional Networks with Adaptive Layer-Instance Normalization for Image-to-Image Translation (ICLR 2020)

v2ray_bin

梅林380 固件的魔改科学上网插件

verilog-perl

Verilog parser, preprocessor, and related tools for the Verilog-Perl package

virtio

Virtio implementation in SystemVerilog

virtio-fpga

A platform for emulating Virtio devices with FPGAs

virtio-fpga-bridge

Virtio front-end and back-end bridge, implemented with FPGA.

xcryptcore

Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)

zcash-fpga

Zcash FPGA acceleration engine