zhuyanzhen1/prirv32

这是我设计的第一个RV32内核，这个内核只打算实现RV32I指令集架构，对标8051及ARM Cortex-M0内核。This is the first RV32 core I designed. This core only intends to implement the RV32I instruction set architecture, which is aimed at the 8051 and ARM Cortex-M0 cores.

priRV32

        

    priRV32 is a kernel that can implement the RV32I sub-instruction set architecture and RV machine mode. This kernel is currently under development. The naming of modules and variables in this kernel code refers to the naming method in picoRV32, and there are many similarities in the naming of variables. In addition, in order to reduce the development time, the code of the peripheral part was directly packaged and used from the code provided by the Alinx FPGA development board. This kernel is for learning purposes only, and I am not responsible for any use in other scenarios.

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Preface

    In the first half of the semester, I was studying at home due to the epidemic, and I saw RISC-V-related books sold on Taobao. Since then, the idea of ​​"writing RISC-V processors from scratch" has continued to appear in my mind. At that time, I didn't understand the basic knowledge of computers (I only read the authoritative guide for the ARM Cortex-M3 core). Sophomore year, I have been supplementing computer-related knowledge, including computer system structure, computer composition principle, data structure, Linux kernel and so on. Now that the junior year transfers to integrated circuits, there is a course of computer system structure, so I want to take this opportunity to implement a simple RV kernel.
    Since this is the first RV32 core I designed, considering my low level, this core only intends to implement the RV32I instruction set architecture, the core frequency is 36MHz, and it is against the current 8051 and ARM Cortex-M0 cores. In terms of combined functions, the kernel is named priRV32, which means "primary RV32 kernel". It is the first time to write a relatively large-scale project, and there are many immature and shortcomings in the language specification and implementation, and I invite developers Haihan.

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Develop Environment

• IDE: Visual Studio Code 1.62.1 & Quartus Prime 20.1 Lite Edition
• OS: Windows_NT x64 10.0.19041
• Simulator: icarus verilog 11.0

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Directory Structure

• core: The source code files related to the priRV32 kernel, which mainly include the instruction fetching and decoding unit and the execution write-back unit.
• fpga: FPGA project file based on Quartus Lite Edition integrated development environment.
• periph: Some source files of simple peripheral interfaces.
  • uart: source file of UART serial peripherals.
• tb: Test script files for the kernel and peripherals.

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License

Affiliation：AcmeTech
Author: Zhu Yanzhen
Maintainer：YanzhenZhu, [email protected]

    The source code is released under a AGPL-3.0 License.The product has been tested under Windows 10 and Ubuntu 18.04 and 20.04. This is research code, expect that it changes often and any fitness for a particular purpose is disclaimed.