Comments (3)
The file is not missing, it just doesn't exist. There is no doc/src/spec.tex file (yet).
I've tossed around whether or not I want to write one, but instead I've tried to place more extensive file headers containing usage information. Building a spec.pdf file at this point would just duplicate what's already in either the source files or the various README's. Those should each have extensive (and sufficient) information in them.
Please let me know if you are looking for something particular and not finding it.
Dan
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OK. I'll close this issue. My goal is understand some of the basics of the libraries, wishbone to AXI and create a python generator similar to . wb_intercon. Also what a great library, very good work.
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I've used AutoFPGA as a bus generator with these files. They're really designed for that purpose, although they should work with any other core generator.
Be careful, when using wb_intercon, the Wishbone files here use Wishbone pipeline, not Classic. There is a bridge here to go from pipeline to classic--although your performance will go down should you use it.
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Related Issues (20)
- illegal localparam in list of parameters HOT 2
- Icarus-verilog elaboration failed in axixbar.v HOT 1
- Which yosys version should I use? HOT 2
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- skid buffer proved by smtbmc but fail by abc pdr HOT 3
- axi2axilite HOT 3
- Eliminate Ports S_AXI_C* Until Supported by AutoFPGA HOT 4
- AXIS2MM & WUSER bits/byte causes critical warning in Vivado HOT 3
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- Possible enhancement: add AWCACHE parameter to axis2mm HOT 2
- `default_nettype none breaks vivado global synthesis HOT 10
- Enhacement: Sync only on TLAST option for axis2mm HOT 10
- Is the OPT_NONESEL option currently the same as the multiple slaves? HOT 1
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- Missing LICENSE file HOT 3
- Question regarding AW / W channel dependencies HOT 8
- Whether the situation crossing 4K boundary has been handled in AXIDMA? HOT 2
- axim2wbsp.v: has different data endianness for write and read channels HOT 1
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