Comments (1)
Fixed in 8ae4431
from wb2axip.
Related Issues (20)
- Which yosys version should I use? HOT 2
- `s2mm` doesn't update address or len external registers HOT 2
- skid buffer proved by smtbmc but fail by abc pdr HOT 3
- axi2axilite HOT 3
- Eliminate Ports S_AXI_C* Until Supported by AutoFPGA HOT 4
- AXIS2MM & WUSER bits/byte causes critical warning in Vivado HOT 3
- Kicking off a transfer with AXIS2MM HOT 16
- Vivado Block design, local param, and axixbar HOT 2
- Possible enhancement: add AWCACHE parameter to axis2mm HOT 2
- `default_nettype none breaks vivado global synthesis HOT 10
- Enhacement: Sync only on TLAST option for axis2mm HOT 10
- Is the OPT_NONESEL option currently the same as the multiple slaves? HOT 1
- File 'faxi_valaddr.v' is missing HOT 1
- Missing LICENSE file HOT 3
- Question regarding AW / W channel dependencies HOT 8
- Whether the situation crossing 4K boundary has been handled in AXIDMA? HOT 2
- axim2wbsp.v: has different data endianness for write and read channels HOT 1
- axisafety.v in ZYNQ Ultrascale+ works for read operations, but not for write operations HOT 11
- is the axiclk can be used in the axi lite scenario HOT 4
- Why does the axixclk module has no wid input/output? HOT 2
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