add support for riscv64

[yuzibo]

add support for riscv64

[flobernd]

Hi there,

thanks for submitting your patch 🙂 We will try to integrate this upstream.

Pasting the patch here for reference:

--- a/include/Zycore/Defines.h
+++ b/include/Zycore/Defines.h
@@ -131,6 +131,8 @@
 #   define ZYAN_AARCH64
 #elif defined(_M_ARM) || defined(_M_ARMT) || defined(__arm__) || defined(__thumb__)
 #   define ZYAN_ARM
+#elif defined(_M_RISCV64) || defined(__riscv) && __riscv_xlen == 64
+#   define ZYAN_RISCV64
 #elif defined(__EMSCRIPTEN__)
     // Nothing to do, `ZYAN_EMSCRIPTEN` is both platform and arch macro for this one.
 #else
--- a/src/Format.c
+++ b/src/Format.c
@@ -423,7 +423,7 @@
 
 ZyanStatus ZyanStringAppendDecU(ZyanString* string, ZyanU64 value, ZyanU8 padding_length)
 {
-#if defined(ZYAN_X64) || defined(ZYAN_AARCH64)
+#if defined(ZYAN_X64) || defined(ZYAN_AARCH64) || defined(ZYAN_RISCV64)
     return ZyanStringAppendDecU64(string, value, padding_length);
 #else
     // Working with 64-bit values is slow on non 64-bit systems
@@ -464,7 +464,7 @@
 ZyanStatus ZyanStringAppendHexU(ZyanString* string, ZyanU64 value, ZyanU8 padding_length,
     ZyanBool uppercase)
 {
-#if defined(ZYAN_X64) || defined(ZYAN_AARCH64)
+#if defined(ZYAN_X64) || defined(ZYAN_AARCH64) || defined(ZYAN_RISCV64)
     return ZyanStringAppendHexU64(string, value, padding_length, uppercase);
 #else
     // Working with 64-bit values is slow on non 64-bit systems

[flobernd]

@athre0z We should probably as well introduce a generic ZYAN_ARCH64 (open for better name suggestions). Same for 32-bit environments.

[athre0z]

Yeah, was thinking the same thing when reading the patch: let's do that! Maybe ZYAN_64_BIT_ARCH? ZYAN_ARCH64 would be fine as well if ARM folks hadn't decided to call their ISA AARCH64... 😅

[yuzibo]

Hi, many thanks for working on this.
Please feel free to tell me if there need me to do some tests on real riscv64 hardware(Unmatched board). Or:
Applying for accessing to real riscv64 hardware(Unmatched board also) from here:
https://github.com/plctlab/riscv-lab-access