apertus-open-source-cinema/naps

An experiment for building gateware for the axiom micro / beta using amaranth-hdl

naps - The Relaxed Amaranth Packages Collection

Building Blocks & Tools for FPGA Design with Python & Amaranth HDL. Mostly a place to experiment and figure out how to build things. Also the incubator for the future AXIOM Beta camera gateware & the home of the current AXIOM micro gateware.

This repo contains:

• Prototypes of the upcoming Amaranth data types PackedStruct and Interface (here called Bundle) (in src/lib/data_structure/)
• A stream Abstraction with various building Blocks: (in src/lib/stream/)
  • FIFOs
  • A gearbox for changing the width
  • Helpers for building other Stream cores
  • Miscellaneous Debug and Inspection tools
• various Amaranth cores (in src/lib/) for:
  • AXI and AXI Lite including a Buffer reader and Writer
  • A CSR bank that can be wired to an AXI bus
  • HDMI (currently the DVI subset; derived from Litevideo)
  • A HISPI reciever (for the use with aptina / onsemi image sensors)
  • A core for streaming data over USB3 using the ft601
  • Some utility video processing (like debayering)
  • …
• tools for gluing together SOCs (currently supports the Xilinx Zynq and JTAG based plattoforms) in src/soc/
  • Making heavy use of Amaranth HDL Platform abstractions (wrapping existing plattforms)
  • Provides a bus agnostic way to describe (low speed) peripherals
  • Emits Python code that can be used to access the designs CSRs (“pydriver”)
  • Generate devicetree overlays for loading linux device drivers
  • pack “fatbitstreams” that bundle setup logic, drivers and the bitstream
  • there is a Poster about the naps soc infrastructure.
• platform definitions for both the AXIOM Beta and the AXIOM Micro in src/devices/
• a variety of other smaller half-working experiments in src/experiments/
  • linux framebuffer HDMI output
  • USB3 Plugin module gateware (wip)
  • AXIOM micro camera gateware (wip)
  • test gateware to test connectors for their ability to transmit high speed data (via a loopback test)
  • test gateware for the axi writer & reader

Installation

Installing

naps's Issues

URL on the repo is 404

The URL on this repository goes to https://apertus-open-source-cinema.github.io/nmigen-gateware/intro.html which seems to be a 404. In fact the docs at https://apertus-open-source-cinema.github.io/ seem to be non-existent?

Rework peripheral addresses

To simplify code and reduce the possibility for bugs, we want to rework the way addresses and the memorymap works.

1. Addresses should be in units of the bus word size, this means 32bits for both AXI and JTAG
2. This means a logical to physical conversion routine is needed for things like the HardwareProxy (and vice versa)
3. This means now all unaligned memory accesses are impossible

Invalid settings in DDR OSERDESE2?

https://github.com/apertus-open-source-cinema/nmigen-gateware/blob/4514d62f1b802f4f73e73311c5696dfb4118c246/src/cores/primitives/xilinx_s7/io.py#L34

This is invalid, and generates warnings in synthesis. However, it seems like this is copied from litevideo, which I assume is functional. Zynq-7000 technical reference manual refers to UG471, which defines in Table 3-8, that for given OQ and TQ, DATA_WIDTH and TRISTATE_WIDTH are only allowed to be 4. OSerdes10 is only used in the hdmi output core. Has that been tested to work? My Z7020 fails to be detected as a valid HDMI source with a slightly modified hdmi_test experiment, and hard-wired RGB values in the modified hdmi core. It's possible that Vivado overrides the values to be 4 and everything is fine, but considering memseting mmapped HDMI buffers in DDR RAM hangs my Zynq, I would think this might be a part of the problem... but maybe it's not, since it's a verbatim rewrite of the relevant source code in litevideo.

Add License

This Repository needs a license. I would vote fro AGPL-3.0.
Is that okay for you @rroohhh @ekliptik ?

Improve caching

There are some additional things that should go into the cache key:

1. clock constraints
2. NMIGEN_* environment variables
3. maybe the nmigen, nmigen-boards, ... version