Topic: soc Goto Github
Some thing interesting about soc
Some thing interesting about soc
soc,常见的攻击行为监测特征及方法,涵盖端点和流量,未包含PowerShell和Sysmon。预祝运营生活愉快!
User: 0x783kb
Home Page: https://0x783kb.github.io/Security-Operation-Book/
soc,Given a job title and job description, the algorithm assigns a standard occupational classification (SOC) code to the job.
User: aeturrell
Home Page: https://occupationcoder.readthedocs.io/
soc,My own cybersecurity research talks/slides
User: akechishiro
soc,Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
User: aleksandarkostovic
soc,An experiment for building gateware for the axiom micro / beta using amaranth-hdl
Organization: apertus-open-source-cinema
Home Page: https://apertus-open-source-cinema.github.io/naps/intro.html
soc,Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedded programs targeted at the microprocessor to control the peripherals
Organization: arm-university
soc,This repo contains all the necessary design and fabrication files for the Seeed Studio LoRa-E5 based Penguino Feather breakout board.
User: azerimaker
Home Page: https://makertronika.com/
soc,Given a job title and job description, the algorithm assigns a standard occupational classification (SOC) code to the job.
Organization: bank-of-england
soc,Pointing cybersecurity teams to thousands of detection rules and offensive security tests aligned with common attacker techniques
User: controlcompass
Home Page: https://controlcompass.github.io
soc,:star: :star: Distributed tcpdump for cloud native environments :star: :star:
Organization: deepfence
soc,An AXI4 crossbar implementation in SystemVerilog
User: dpretet
soc,Microsoft Sentinel SOC Operations
User: eshlomo1
soc,gem5 simulator with a gpgpu+graphics GPU model
Organization: gem5-graphics
soc,Hisilicon SDK for SoC Hi3798Mv100 / Hi3798Cv200 / Hi3798Mv200 / Hi3798Mv300.
User: jasonfreelab
soc,Awesome Security lists for SOC/CERT/CTI
User: mthcht
soc,Purpleteam scripts simulation & Detection - trigger events for SOC detections
User: mthcht
soc,Awesome list of keywords and artifacts for Threat Hunting sessions
User: mthcht
Home Page: https://mthcht.github.io/ThreatHunting-Keywords/
soc,Scripts to make life as an NUS student better and easier.
Organization: nusmodifications
soc,PatrowlHears - Vulnerability Intelligence Center / Exploits
Organization: patrowl
Home Page: https://patrowlhears.io
soc,学习安全运营的记录 | The knowledge base of security operation
User: satan1a
Home Page: https://wiki.y1ng.org
soc,Contains information about accepted GSoC 2017 Projects across various organizations along with the proposals.
User: saurabhshri
soc,A really good DFIR automation for collecting and analyzing evidence designed for cybersecurity professionals.
Organization: securityjoes
Home Page: http://github.com/YosfanEilay
soc,MasterParser is a powerful DFIR tool designed for analyzing and parsing Linux logs
Organization: securityjoes
Home Page: https://github.com/YosfanEilay
soc,Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
User: sergeykhbr
Home Page: http://sergeykhbr.github.io/riscv_vhdl/
soc,:computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
User: stnolting
soc,:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
User: stnolting
Home Page: https://neorv32.org
soc,Companion Jupyter Notebooks for the RFSoC-Book.
Organization: strath-sdr
Home Page: https://www.rfsocbook.com/
soc,Tenzir is the data pipeline engine for security teams.
Organization: tenzir
Home Page: https://docs.tenzir.com
soc,The SOC Analysts all-in-one CLI tool to automate and speed up workflow.
User: theresafewconors
soc,Ransomware Detection using Machine Learning with eBPF for Linux.
User: tomasphilippart
Home Page: http://ebpfangel.philippart.me/
soc,An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Organization: ucb-bar
Home Page: https://chipyard.readthedocs.io/en/stable/
soc,A Chisel RTL generator for network-on-chip interconnects
Organization: ucb-bar
Home Page: http://constellation.readthedocs.io
soc,DDWPasteRecon tool will help you identify code leak, sensitive files, plaintext passwords, password hashes. It also allow member of SOC & Blue Team to gain situational awareness of the organisation's web exposure on the pastesites. It Utilises Google's indexing of pastesites to gain targeted intelligence of the organisation. Blue & SOC teams can collect and analyse data from these indexed pastesites to better protect against unknown threats.
User: viralmaniar
soc,An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC,包含一个简单且可扩展的外设总线。
User: wangxuan95
Home Page: https://gitee.com/wangxuan95/USTC-RVSoC
soc, CMU 18545 FPGA project -- Multi-channel ultrasound data acquisition and beamforming system.
User: waynezv
soc,HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve
User: wilsonchen003
soc,The extensible bootloader for embedded system with application engine, write once, run everywhere.
Organization: xboot
Home Page: https://xboot.github.io
soc,Vitis_Accel_Examples
Organization: xilinx
Home Page: http://xilinx.github.io/Vitis_Accel_Examples/
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