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SoC based on VexRiscv and ICE40 UP5K

License: MIT License

Scala 43.60% Makefile 2.55% Assembly 0.55% Verilog 9.58% C 31.15% Python 0.18% CMake 0.01% Tcl 10.15% Shell 1.64% SystemVerilog 0.28% VHDL 0.31%
riscv rtl soc

saxonsoc's Introduction

About SpinalHDL

SpinalHDL is:

  • A language to describe digital hardware
  • Compatible with EDA tools, as it generates VHDL/Verilog files
  • Much more powerful than VHDL, Verilog, and SystemVerilog in its syntax and features
  • Much less verbose than VHDL, Verilog, and SystemVerilog
  • Not an HLS, nor based on the event-driven paradigm
  • Only generates what you asked it in a one-to-one way (no black-magic, no black box)
  • Not introducing area/performance overheads in your design (versus a hand-written VHDL/Verilog design)
  • Based on the RTL description paradigm, but can go much further
  • Allowing you to use Object-Oriented Programming and Functional Programming to elaborate your hardware and verify it
  • Free and can be used in the industry without any license

Links

English: Join the chat at https://gitter.im/SpinalHDL/SpinalHDL 中文: Join the chat at https://gitter.im/SpinalHDL-CN/community

Get it

SpinalHDL is simply a set of Scala libraries. Include them into your project and you're good to go! If you're unsure about what to do, simply clone one of our example projects (see links above).

SBT (Scala build tool)

scalaVersion := "2.11.12"

libraryDependencies ++= Seq(
  "com.github.spinalhdl" % "spinalhdl-core_2.11" % "latest.release",
  "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "latest.release",
  compilerPlugin("com.github.spinalhdl" % "spinalhdl-idsl-plugin_2.11" % "latest.release")
)

You can force SBT to pick a specific SpinalHDL version by replacing latest.release with a specific version. See the SpinalHDL SBT Template project's build.sbt file for a full SBT example.

Gradle

repositories {
	mavenCentral()
}

dependencies {
	compile group: 'com.github.spinalhdl', name: 'spinalhdl-core_2.11', version: '1.6.4'
	compile group: 'com.github.spinalhdl', name: 'spinalhdl-lib_2.11', version: '1.6.4'
}

Mill(Build Tool)

import mill._
import mill.scalalib._

object MySpinalModule extends ScalaModule {
  def scalaVersion = "2.11.12"

  def ivyDeps = Agg(
    ivy"com.github.spinalhdl::spinalhdl-core:1.6.4",
    ivy"com.github.spinalhdl::spinalhdl-lib:1.6.4",
  )

  def scalacPluginIvyDeps = Agg(ivy"com.github.spinalhdl::spinalhdl-idsl-plugin:1.6.4")
}

JAR

https://oss.sonatype.org/content/groups/public/com/github/spinalhdl/spinalhdl-core_2.11/
https://oss.sonatype.org/content/groups/public/com/github/spinalhdl/spinalhdl-lib_2.11/

The files are available on Maven as well.

Change logs

https://github.com/SpinalHDL/SpinalHDL/tags

License

The SpinalHDL core is using the LGPL3 license while SpinalHDL lib and others are using the MIT license. That's for the formalities. But there are some practical statements implied by those licenses:

Your freedoms are:

  • You can use SpinalHDL core and lib in your closed/commercial projects.
  • The generated RTL is yours (.vhd/.v files)
  • Your hardware description is yours (.scala files)

Your obligations (and my wish) are:

  • If you modify the SpinalHDL core (the compiler itself), please, share your improvements.

Also, SpinalHDL is provided "as is", without warranty of any kind.

saxonsoc's People

Contributors

dolu1990 avatar dpavlin avatar fredrikaleksander avatar kost avatar lawrie avatar michg avatar roman3017 avatar sebastien-riou avatar surabibio avatar svancau avatar

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saxonsoc's Issues

software compile fail

Hi
I use this command to compile the demo code.
SaxonSoc/software/standalone/blinkRgb$make BSP=FomuMinimal
and it report compile fail, here is the output detail。
it seem that the program is rv32i but it use the riscv64 libc.a (64-bit), so link failed.
can somebody help me figure out how to solve this problem :(

mkdir -p build//home/ubuntu/oss/SaxonSoc/software/standalone/blinkRgb/src/
riscv64-unknown-elf-gcc -c -I../../../bsp/FomuMinimal/include -I../../../bsp/FomuMinimal/app -Os -march=rv32i -mabi=ilp32 -DUSE_GP -I../include -I../driver -o build//home/ubuntu/oss/SaxonSoc/software/standalone/blinkRgb/src/main.o src/main.c
mkdir -p build//home/ubuntu/oss/SaxonSoc/software/standalone/common/
riscv64-unknown-elf-gcc -c -I../../../bsp/FomuMinimal/include -I../../../bsp/FomuMinimal/app -Os -march=rv32i -mabi=ilp32 -DUSE_GP -I../include -I../driver -o build//home/ubuntu/oss/SaxonSoc/software/standalone/common/start.o ../common/start.S
riscv64-unknown-elf-gcc -I../../../bsp/FomuMinimal/include -I../../../bsp/FomuMinimal/app -Os -march=rv32i -mabi=ilp32 -DUSE_GP -I../include -I../driver -o build/blinkRgb.elf build//home/ubuntu/oss/SaxonSoc/software/standalone/blinkRgb/src/main.o build//home/ubuntu/oss/SaxonSoc/software/standalone/common/start.o -march=rv32i -mabi=ilp32 -lc -nostdlib -lgcc -nostartfiles -ffreestanding -Wl,-Bstatic,-T,../../../bsp/FomuMinimal/linker/default.ld,-Map,build/blinkRgb.map,--print-memory-usage
/opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/9.2.0/../../../../riscv64-unknown-elf/bin/ld: /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/9.2.0/../../../../riscv64-unknown-elf/lib/libc.a(lib_a-init.o): ABI is incompatible with that of the selected emulation:
target emulation elf64-littleriscv' does not match elf32-littleriscv'
/opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/9.2.0/../../../../riscv64-unknown-elf/bin/ld: failed to merge target specific data of file /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/9.2.0/../../../../riscv64-unknown-elf/lib/libc.a(lib_a-init.o)
/opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/9.2.0/../../../../riscv64-unknown-elf/bin/ld: build/blinkRgb.elf(.text): relocation ".L5+0x0 (type R_RISCV_BRANCH)" goes out of range
/opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/9.2.0/../../../../riscv64-unknown-elf/bin/ld: /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/9.2.0/../../../../riscv64-unknown-elf/lib/libc.a(lib_a-init.o): file class ELFCLASS64 incompatible with ELFCLASS32
/opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/9.2.0/../../../../riscv64-unknown-elf/bin/ld: final link failed: file in wrong format
collect2: error: ld returned 1 exit status
../common/standalone.mk:31: recipe for target 'build/blinkRgb.elf' failed
make: *** [build/blinkRgb.elf] Error 1

DMA from peripherals?

Is it possible to DMA from peripheral to memory? I see there is the DmaApbBmbGenerator commented out, which looks like it would be for this purpose.

in this case I would like the ability to DMA from SPI to memory, which would require DMA trigger on SPI recieve.

Support for multiple SoC

I would like to use 2 SoC. (e.g one exclusively for WiFi and another exclusively for Data Acquisition) I am able to get 2 Verilog files but am unable to synthesis them due to Verilog Error: (VERI-1206) overwriting previous definition of module.
The work around is rename the duplicate modules (e.g module VexRiscv to wifi_VexRiscv and daq_VexRiscv ...) Is there a way to generate modules with unique names.

Reusing FPGA pins for GPIO and other peripherals

For microcontrollers and systems like Arduino, it is common for the same pins to be used for GPIO and one or more other peripherals. For the output pins, a mux is typically used to switch the pins between use by the GPIO and the other peripherals.

It would be useful if, as part of the definition of the input/output ports of a peripheral, that a mapping onto GPIO pins could be specified along with the muxes to switch the pins,

As the GPIO peripheral uses a tri-state array, the C driving code for a peripheral would need to set the pins used by the peripheral to input or output as appropriate (using the GPIO writeEnable register), and to sets bits in a register to switch the muxes. It would be useful if a C header file were generated that gave the mapping between the peripheral pins and the GPIO pins and specified the mux register addresses and bit offsets..

SRAM support?

Could you give any advice on how to implement an SRAM controller?

I see there is the BmbSramGenerator.scala in deprecated but this is not compatible with the latest branch and I do not have enough knowledge of any of this to know quite how to migrate it.

Help with this much appreciated.

Standard SPI available?

Hi,
How do I set up a standard SPI with data-width as 1 (i.e 1 MOSI and 1 MISO signal)
BmbSpiGenerator() seems to work only when SpiXdrParameter.dataWidth is 2 or more...

How can I get a VGA signal in addition to HDMI?

Hi,

I am continuing to learn SaxonSoc's Minimal sample.
I've got VGA (HDMI) from SDRAM working.
I want to output to HDMI, but also externally extract the VGA signal for LCD.

I think SaxonSoC automatically creates the inputs and outputs with InOutWrapper.
In this case, how should I describe it?

ICESugarProMinimal.scala

Support for Arty A7 100t

Can we have support for synthesising necessary files for the 100t variant of digilent arty kit?

Vexriscv snapshot unresolved dependency path during assembly

Hello,

It seems that a vexriscv SNAPSHOT is missing from https://repo1.maven.org/maven2/default/.
Or maybe my install is faulty ?

thales@XPS-15-9560:~/saxonsoc$ sbt assembly
[info] welcome to sbt 1.4.7 (Private Build Java 1.8.0_222)
[info] loading settings for project global-plugins from idea.sbt ...
[info] loading global plugins from /home/thales/.sbt/1.0/plugins
[info] loading settings for project saxonsoc-build from plugins.sbt ...
[info] loading project definition from /home/thales/saxonsoc/project
[info] loading settings for project root from build.sbt ...
[info] set current project to SaxonSoc (in build file:/home/thales/saxonsoc/)
[info] Updating 
[info] Resolved  dependencies
[warn] 
[warn] 	Note: Unresolved dependencies path:
[error] sbt.librarymanagement.ResolveException: Error downloading default:vexriscv_2.11:0.1.0-SNAPSHOT
[error]   Not found
[error]   Not found
[error]   not found: /home/thales/.ivy2/localdefault/vexriscv_2.11/0.1.0-SNAPSHOT/ivys/ivy.xml
[error]   not found: https://repo1.maven.org/maven2/default/vexriscv_2.11/0.1.0-SNAPSHOT/vexriscv_2.11-0.1.0-SNAPSHOT.pom
[error] 	at lmcoursier.CoursierDependencyResolution.unresolvedWarningOrThrow(CoursierDependencyResolution.scala:258)
[error] 	at lmcoursier.CoursierDependencyResolution.$anonfun$update$38(CoursierDependencyResolution.scala:227)
[error] 	at scala.util.Either$LeftProjection.map(Either.scala:573)
[error] 	at lmcoursier.CoursierDependencyResolution.update(CoursierDependencyResolution.scala:227)
[error] 	at sbt.librarymanagement.DependencyResolution.update(DependencyResolution.scala:60)
[error] 	at sbt.internal.LibraryManagement$.resolve$1(LibraryManagement.scala:53)
[error] 	at sbt.internal.LibraryManagement$.$anonfun$cachedUpdate$12(LibraryManagement.scala:103)
[error] 	at sbt.util.Tracked$.$anonfun$lastOutput$1(Tracked.scala:73)
[error] 	at sbt.internal.LibraryManagement$.$anonfun$cachedUpdate$20(LibraryManagement.scala:116)
[error] 	at scala.util.control.Exception$Catch.apply(Exception.scala:228)
[error] 	at sbt.internal.LibraryManagement$.$anonfun$cachedUpdate$11(LibraryManagement.scala:116)
[error] 	at sbt.internal.LibraryManagement$.$anonfun$cachedUpdate$11$adapted(LibraryManagement.scala:97)
[error] 	at sbt.util.Tracked$.$anonfun$inputChangedW$1(Tracked.scala:219)
[error] 	at sbt.internal.LibraryManagement$.cachedUpdate(LibraryManagement.scala:130)
[error] 	at sbt.Classpaths$.$anonfun$updateTask0$5(Defaults.scala:3486)
[error] 	at scala.Function1.$anonfun$compose$1(Function1.scala:49)
[error] 	at sbt.internal.util.$tilde$greater.$anonfun$$u2219$1(TypeFunctions.scala:62)
[error] 	at sbt.std.Transform$$anon$4.work(Transform.scala:68)
[error] 	at sbt.Execute.$anonfun$submit$2(Execute.scala:282)
[error] 	at sbt.internal.util.ErrorHandling$.wideConvert(ErrorHandling.scala:23)
[error] 	at sbt.Execute.work(Execute.scala:291)
[error] 	at sbt.Execute.$anonfun$submit$1(Execute.scala:282)
[error] 	at sbt.ConcurrentRestrictions$$anon$4.$anonfun$submitValid$1(ConcurrentRestrictions.scala:265)
[error] 	at sbt.CompletionService$$anon$2.call(CompletionService.scala:64)
[error] 	at java.util.concurrent.FutureTask.run(FutureTask.java:266)
[error] 	at java.util.concurrent.Executors$RunnableAdapter.call(Executors.java:511)
[error] 	at java.util.concurrent.FutureTask.run(FutureTask.java:266)
[error] 	at java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1149)
[error] 	at java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:624)
[error] 	at java.lang.Thread.run(Thread.java:748)
[error] (update) sbt.librarymanagement.ResolveException: Error downloading default:vexriscv_2.11:0.1.0-SNAPSHOT
[error]   Not found
[error]   Not found
[error]   not found: /home/thales/.ivy2/localdefault/vexriscv_2.11/0.1.0-SNAPSHOT/ivys/ivy.xml
[error]   not found: https://repo1.maven.org/maven2/default/vexriscv_2.11/0.1.0-SNAPSHOT/vexriscv_2.11-0.1.0-SNAPSHOT.pom
[error] Total time: 2 s, completed 3 févr. 2022 17:40:52

SVD register descriptions

This was mentioned on the ulx3s discord by thorns514 and I thought it was a good idea. For bare-metal programming in rust and potentially other languages, it would be useful if there were machine-parseable register descriptions in SVD format.

I'm not sure to how what point these could be automatically generated dynamically. But a start could be the Linux dts which provides the peripherals base offsets and interrupt numbers.

Ulx3s with Ethernet?

Hi again,

The running Linux image shows eth0 - is it possible to connect a LAN8720 Microchip RMII or ENC28J60 Adapter? if so, where can I find the correct pin-out?

Thanks

usb pmod

Hello,

Couple of weeks, I saw this video https://www.youtube.com/watch?v=K5Vv32O9g7Q
I would like to run this demo on my side, I have an Arty7 35t, pmod VGA and pmod SDcard.
On the video, I don't see what is the pmod use for USB.
Could you please tell me what is the pmod used?
Regards

Generation of a C header with I/O addresses

The memory bus addresses and offsets used by each peripheral are part of the definition of SaxonSoc or a CustomSoc, but are also needed in the C programs that drive those peripherals. It would be useful if a C header file containing those addresses and offsets could be generated.

mtvec read value via debug

Not sure if the issue is hardware or software. The first read via GDB returns a wrong value (always the same across multiple trials on FPGA). I get the correct value after a stepi (with an instruction which does not touch mtvec).

Reading symbols from build/Matryoshka/testRam.elf...
(gdb) set remotetimeout 10000
(gdb) set arch riscv:rv32
The target architecture is assumed to be riscv:rv32
(gdb) target extended-remote :3333
Remote debugging using :3333
0x20a00000 in ?? ()
(gdb) load
Loading section .init, size 0x94 lma 0x10a80000
Loading section .text, size 0x2006 lma 0x10a80094
Loading section .eh_frame, size 0x50 lma 0x10a8209c
Loading section .data, size 0x734 lma 0x10a820ec
Start address 0x10a80000, load size 10270
Transfer rate: 10 KB/sec, 2567 bytes/write.
(gdb) info registers $pc
pc             0x10a80000	0x10a80000 <_start>
(gdb) info registers $mtvec
mtvec          0x0	0
(gdb) continue
Continuing.
^C
Program received signal SIGINT, Interrupt.
0x10a811b8 in satl_master_fuzzing ()
(gdb) info registers $pc   
pc             0x10a811b8	0x10a811b8 <satl_master_fuzzing+240>
(gdb) info registers $mtvec
mtvec          0x20a0114c	547361100
(gdb) info registers $mtvec
mtvec          0x20a0114c	547361100
(gdb) disassemble /r
...
   0x10a8115e <+150>:	99 a0	j	0x10a811a4 <satl_master_fuzzing+220>
   0x10a81160 <+152>:	b9 e8	bnez	s1,0x10a811b6 <satl_master_fuzzing+238>
   0x10a81162 <+154>:	73 29 00 b0	csrr	s2,mcycle
   0x10a81166 <+158>:	b3 b7 29 01	sltu	a5,s3,s2
   0x10a8116a <+162>:	33 07 39 41	sub	a4,s2,s3
...
   0x10a811b6 <+238>:	82 94	jalr	s1
=> 0x10a811b8 <+240>:	4d d5	beqz	a0,0x10a81162 <satl_master_fuzzing+154>
   0x10a811ba <+242>:	05 45	li	a0,1
   0x10a811bc <+244>:	e5 b7	j	0x10a811a4 <satl_master_fuzzing+220>
   0x10a811be <+246>:	e3 72 ea f6	bgeu	s4,a4,0x10a81122 <satl_master_fuzzing+90>
   0x10a811c2 <+250>:	65 bf	j	0x10a8117a <satl_master_fuzzing+178>
End of assembler dump.
(gdb) stepi
0x10a81162 in satl_master_fuzzing ()
(gdb) info registers $mtvec
mtvec          0x10a8084a	279447626

4 CPU fails in buildroot (dts)

Hi,
Managed to build a 2 CPU System fine but any attempt to build with 4 CPUs fails while generating linux.dts

SAXON_CPU_COUNT=4 saxon_buildroot
.....
DTC arch/riscv/boot/dts/linux.dtb
Error: /development/Ulx3sSmp/buildroot-spinal-saxon/boards/common/dts/linux_cpu.dts:55.25-26 syntax error
FATAL ERROR: Unable to parse input tree
make[3]: *** [scripts/Makefile.lib:326: arch/riscv/boot/dts/linux.dtb] Error 1
make[2]: *** [Makefile:1338: linux.dtb] Error 2
make[1]: *** [package/pkg-generic.mk:250: /development/Ulx3sSmp/buildroot-build/build/linux-spinal-v5.10.1/.stamp_built] Error 2
make: *** [Makefile:23: _all] Error 2

Any idea how to fix this? the .dts file doesn't look like it's complete.

Thanks

Attached linux_cpu.dts
linux_cpu.dts.gz

Problem with SdramModel when changing sdram layout

There seems to be a problem with SdramModel. In particular, one can run De1SocLinuxSystemSim without any issues with:

sbt "runMain saxon.board.terasic.De1SocLinuxSystemSim"

However, if one tries to change existing sdram layout from IS42x320D to either MT48LC16M16A2 or W9825G6JH6 one gets this exception:

[info] WAITING FOR TCP JTAG CONNECTION
[info] SDRAM : MODE REGISTER DEFINITION CAS=3 burstLength=0
[info] *** VexRiscv BIOS ***
[info] *** Supervisor ***
[info] Unknown exception 00000005
[info] machineModeSbi exception

To reproduce, please try this patch:

diff --git a/hardware/scala/saxon/board/terasic/De1SocLinux.scala b/hardware/scala/saxon/board/terasic/De1SocLinux.scala
index 42a7da0..81f5fc3 100644
--- a/hardware/scala/saxon/board/terasic/De1SocLinux.scala
+++ b/hardware/scala/saxon/board/terasic/De1SocLinux.scala
@@ -8,7 +8,7 @@ import spinal.lib.com.uart.UartCtrlMemoryMappedConfig
 import spinal.lib.com.uart.sim.{UartDecoder, UartEncoder}
 import spinal.lib.generator._
 import spinal.lib.io.{Gpio, InOutWrapper}
-import spinal.lib.memory.sdram.IS42x320D
+import spinal.lib.memory.sdram.MT48LC16M16A2
 import spinal.lib.memory.sdram.sim.SdramModel
 
 
@@ -70,8 +70,8 @@ object De1SocLinuxSystem{
     cpu.config.load(VexRiscvConfigs.linux)
     cpu.enableJtag(clockCtrl)
 
-    sdramA.layout.load(IS42x320D.layout)
-    sdramA.timings.load(IS42x320D.timingGrade7)
+    sdramA.layout.load(MT48LC16M16A2.layout)
+    sdramA.timings.load(MT48LC16M16A2.timingGrade7)
 
     uartA.parameter load UartCtrlMemoryMappedConfig(
       baudrate = 115200,

Please let me know if there are any additional changes required when changing sdram layout.

I2C example software

Hello!

Using Efinix version of SaxonSoC (T120F324 devkit), trying to use i2c as master to communicate with plain slave peripheral. Is there an example to communicate SaxonSoC with plain i2c slave?

Thanks
Igor

Document Banana Memory Bus

From your README it says;

The BMB (Banana Memory Bus) which can cover both cached and cacheless SoC without compromises

Do you have any documentation on the BMB and why it can cover both cached and cacheless SoC without compromise.

ULX3S - Synthesis issue

Hi,
I'm trying to rebuild all components as outlined under Build everything of the readme (https://github.com/SpinalHDL/SaxonSoc/blob/dev/bsp/Ulx3sLinuxUboot/README.md)

The software parts work but I stumble while building the bitstream (make in SaxonSoc/hardware/synthesis/ulx3s) It fails consistently with this error:
4.44.22.3. Executing XAIGER backend.
ERROR: Visited AIG node more than once; this could be a combinatorial loop that has not been broken - see Yosys bug 2530
make: *** [makefile:41: bin/toplevel.json] Error 1

So far, I've tried to completely start from scratch, double-checked all pre-requisites, made sure that all pre-requisites are on the latest build etc.

Any Idea what I could do to rectify this?

BTW: how/where do I specify the size of the FPGA (ULX3S comes with different FPGA sizes)?

Thanks

Get SaxonSoC into the SymbiFlow examples / fpga-tool-perf

The SymbiFlow project is slowly getting pretty decent support for the Xilinx Artix 7 part and more specifically the Digilent Arty A7 board. It would be awesome to have a SaxonSoC design in the SymbiFlow Examples repository so we can make sure the design works with the fully open source tooling (we already have a Linux + LiteX with VexRISCV design example working). I logged chipsalliance/f4pga-examples#74) on the SymbiFlow Examples.

It might also good to get SaxonSoC into the SymbiFlow fpga-tool-perf as a test design -- that way we can track how the performance is improved over time (and how the open tools compares to options like Vivado). (Logged chipsalliance/fpga-tool-perf#278 for that.)

ArtyA7SmpLinux saxon_netlist faild!

Hi,
When I execute Saxon_netlist on the terminal, the command was failed. Below is the log that was run:

chenshux@chenshux:~/ic-projs/ArtyA7SmpLinux/SaxonSoc$ saxon_netlist
bsp cpu1.yaml hardware makefile software
build.sbt ext LICENSE project target
cpu0.yaml formatsdcard.sh linux2sdcard.sh README.md test
[info] welcome to sbt 1.4.7 (Private Build Java 1.8.0_392)
[info] loading settings for project saxonsoc-build from plugins.sbt ...
[info] loading project definition from /home/chenshux/ic-projs/ArtyA7SmpLinux/SaxonSoc/project
[info] loading settings for project root from build.sbt ...
[info] loading settings for project vexriscv-build from plugins.sbt ...
[info] loading project definition from /home/chenshux/ic-projs/ArtyA7SmpLinux/SaxonSoc/ext/VexRiscv/project
[info] loading settings for project root from build.sbt ...
[info] loading settings for project spinalhdl-build from plugin.sbt ...
[info] loading project definition from /home/chenshux/ic-projs/ArtyA7SmpLinux/SaxonSoc/ext/SpinalHDL/project
[info] loading settings for project all from build.sbt ...
[info] set current project to SaxonSoc (in build file:/home/chenshux/ic-projs/ArtyA7SmpLinux/SaxonSoc/)
[info] running (fork) saxon.board.digilent.ArtyA7SmpLinux
[info] [Runtime] SpinalHDL dev git head : 4fd59f09e99b2a3a9e2d5fa00fdad9a536652ae2
[info] [Runtime] JVM max memory : 3492.0MiB
[info] [Runtime] Current date : 2023.12.27 09:51:06
[info] [Progress] at 0.000 : Elaborate components
[info] cpuDecode to fpuDispatch 1
[info] fpuDispatch to cpuRsp 2
[info] cpuWriteback to fpuAdd 1
[info] add 4
[info] mul 5
[info] fma 10
[info] short 2
[info] [Progress] at 3.478 : Checks and transforms
[info] **********************************************************************************************
[info] [Warning] Elaboration failed (21 errors).
[info] Spinal will restart with scala trace to help you to find the problem.
[info] **********************************************************************************************
[info] [Progress] at 3.828 : Elaborate components
[info] cpuDecode to fpuDispatch 1
[info] fpuDispatch to cpuRsp 2
[info] cpuWriteback to fpuAdd 1
[info] add 4
[info] mul 5
[info] fma 10
[info] short 2
[info] [Progress] at 4.995 : Checks and transforms
[error] Exception in thread "main" spinal.core.SpinalExit:
[error] Error detected in phase PhaseAnalog
[error] ********************************************************************************
[error] ********************************************************************************
[error] Assignment data type mismatch
[error] (toplevel/sdramDomain_phyA_logic_phy/??? : Bool) := (toplevel/sdramDomain_phyA_logic_phy/io_sdram_DQ : inout Bits[16 bits])
[error] saxon.board.digilent.ArtyA7SmpLinux$.main(ArtyA7SmpLinux.scala:453)
[error] saxon.board.digilent.ArtyA7SmpLinux.main(ArtyA7SmpLinux.scala)
[error] ********************************************************************************
[error] ********************************************************************************
[error] Assignment data type mismatch
[error] (toplevel/sdramDomain_phyA_logic_phy/??? : Bool) := (toplevel/sdramDomain_phyA_logic_phy/io_sdram_DQ : inout Bits[16 bits])
[error] saxon.board.digilent.ArtyA7SmpLinux$.main(ArtyA7SmpLinux.scala:453)
[error] saxon.board.digilent.ArtyA7SmpLinux.main(ArtyA7SmpLinux.scala)
[error] ********************************************************************************
[error] ********************************************************************************
[error] Assignment data type mismatch
[error] (toplevel/sdramDomain_phyA_logic_phy/??? : Bool) := (toplevel/sdramDomain_phyA_logic_phy/io_sdram_DQ : inout Bits[16 bits])
[error] saxon.board.digilent.ArtyA7SmpLinux$.main(ArtyA7SmpLinux.scala:453)
[error] saxon.board.digilent.ArtyA7SmpLinux.main(ArtyA7SmpLinux.scala)
[error] ********************************************************************************
[error] ********************************************************************************
[error] Assignment data type mismatch
[error] (toplevel/sdramDomain_phyA_logic_phy/??? : Bool) := (toplevel/sdramDomain_phyA_logic_phy/io_sdram_DQ : inout Bits[16 bits])
[error] saxon.board.digilent.ArtyA7SmpLinux$.main(ArtyA7SmpLinux.scala:453)
[error] saxon.board.digilent.ArtyA7SmpLinux.main(ArtyA7SmpLinux.scala)
[error] ********************************************************************************
[error] ********************************************************************************
[error] Assignment data type mismatch
[error] (toplevel/sdramDomain_phyA_logic_phy/??? : Bool) := (toplevel/sdramDomain_phyA_logic_phy/io_sdram_DQ : inout Bits[16 bits])
[error] saxon.board.digilent.ArtyA7SmpLinux$.main(ArtyA7SmpLinux.scala:453)
[error] saxon.board.digilent.ArtyA7SmpLinux.main(ArtyA7SmpLinux.scala)
[error] ********************************************************************************
[error] ********************************************************************************
[error] Assignment data type mismatch
[error] (toplevel/sdramDomain_phyA_logic_phy/??? : Bool) := (toplevel/sdramDomain_phyA_logic_phy/io_sdram_DQ : inout Bits[16 bits])
[error] saxon.board.digilent.ArtyA7SmpLinux$.main(ArtyA7SmpLinux.scala:453)
[error] saxon.board.digilent.ArtyA7SmpLinux.main(ArtyA7SmpLinux.scala)
[error] ********************************************************************************
[error] ********************************************************************************
[error] Assignment data type mismatch
[error] (toplevel/sdramDomain_phyA_logic_phy/??? : Bool) := (toplevel/sdramDomain_phyA_logic_phy/io_sdram_DQ : inout Bits[16 bits])
[error] saxon.board.digilent.ArtyA7SmpLinux$.main(ArtyA7SmpLinux.scala:453)
[error] saxon.board.digilent.ArtyA7SmpLinux.main(ArtyA7SmpLinux.scala)
[error] ********************************************************************************
[error] ********************************************************************************
[error] Assignment data type mismatch
[error] (toplevel/sdramDomain_phyA_logic_phy/??? : Bool) := (toplevel/sdramDomain_phyA_logic_phy/io_sdram_DQ : inout Bits[16 bits])
[error] saxon.board.digilent.ArtyA7SmpLinux$.main(ArtyA7SmpLinux.scala:453)
[error] saxon.board.digilent.ArtyA7SmpLinux.main(ArtyA7SmpLinux.scala)
[error] ********************************************************************************
[error] ********************************************************************************
[error] Assignment data type mismatch
[error] (toplevel/sdramDomain_phyA_logic_phy/??? : Bool) := (toplevel/sdramDomain_phyA_logic_phy/io_sdram_DQ : inout Bits[16 bits])
[error] saxon.board.digilent.ArtyA7SmpLinux$.main(ArtyA7SmpLinux.scala:453)
[error] saxon.board.digilent.ArtyA7SmpLinux.main(ArtyA7SmpLinux.scala)
[error] ********************************************************************************
[error] ********************************************************************************
[error] Assignment data type mismatch
[error] (toplevel/sdramDomain_phyA_logic_phy/??? : Bool) := (toplevel/sdramDomain_phyA_logic_phy/io_sdram_DQ : inout Bits[16 bits])
[error] saxon.board.digilent.ArtyA7SmpLinux$.main(ArtyA7SmpLinux.scala:453)
[error] saxon.board.digilent.ArtyA7SmpLinux.main(ArtyA7SmpLinux.scala)
[error] ********************************************************************************
[error] ********************************************************************************
[error] Assignment data type mismatch
[error] (toplevel/sdramDomain_phyA_logic_phy/??? : Bool) := (toplevel/sdramDomain_phyA_logic_phy/io_sdram_DQ : inout Bits[16 bits])
[error] saxon.board.digilent.ArtyA7SmpLinux$.main(ArtyA7SmpLinux.scala:453)
[error] saxon.board.digilent.ArtyA7SmpLinux.main(ArtyA7SmpLinux.scala)
[error] ********************************************************************************
[error] ********************************************************************************
[error] Assignment data type mismatch
[error] (toplevel/sdramDomain_phyA_logic_phy/??? : Bool) := (toplevel/sdramDomain_phyA_logic_phy/io_sdram_DQ : inout Bits[16 bits])
[error] saxon.board.digilent.ArtyA7SmpLinux$.main(ArtyA7SmpLinux.scala:453)
[error] saxon.board.digilent.ArtyA7SmpLinux.main(ArtyA7SmpLinux.scala)
[error] ********************************************************************************
[error] ********************************************************************************
[error] Assignment data type mismatch
[error] (toplevel/sdramDomain_phyA_logic_phy/??? : Bool) := (toplevel/sdramDomain_phyA_logic_phy/io_sdram_DQ : inout Bits[16 bits])
[error] saxon.board.digilent.ArtyA7SmpLinux$.main(ArtyA7SmpLinux.scala:453)
[error] saxon.board.digilent.ArtyA7SmpLinux.main(ArtyA7SmpLinux.scala)
[error] ********************************************************************************
[error] ********************************************************************************
[error] Assignment data type mismatch
[error] (toplevel/sdramDomain_phyA_logic_phy/??? : Bool) := (toplevel/sdramDomain_phyA_logic_phy/io_sdram_DQ : inout Bits[16 bits])
[error] saxon.board.digilent.ArtyA7SmpLinux$.main(ArtyA7SmpLinux.scala:453)
[error] saxon.board.digilent.ArtyA7SmpLinux.main(ArtyA7SmpLinux.scala)
[error] ********************************************************************************
[error] ********************************************************************************
[error] Assignment data type mismatch
[error] (toplevel/sdramDomain_phyA_logic_phy/??? : Bool) := (toplevel/sdramDomain_phyA_logic_phy/io_sdram_DQ : inout Bits[16 bits])
[error] saxon.board.digilent.ArtyA7SmpLinux$.main(ArtyA7SmpLinux.scala:453)
[error] saxon.board.digilent.ArtyA7SmpLinux.main(ArtyA7SmpLinux.scala)
[error] ********************************************************************************
[error] ********************************************************************************
[error] Assignment data type mismatch
[error] (toplevel/sdramDomain_phyA_logic_phy/??? : Bool) := (toplevel/sdramDomain_phyA_logic_phy/io_sdram_DQ : inout Bits[16 bits])
[error] saxon.board.digilent.ArtyA7SmpLinux$.main(ArtyA7SmpLinux.scala:453)
[error] saxon.board.digilent.ArtyA7SmpLinux.main(ArtyA7SmpLinux.scala)
[error] ********************************************************************************
[error] ********************************************************************************
[error] Assignment data type mismatch
[error] (toplevel/sdramDomain_phyA_logic_phy/??? : Bool) := (toplevel/sdramDomain_phyA_logic_phy/io_sdram_DQS : inout Bits[2 bits])
[error] saxon.board.digilent.ArtyA7SmpLinux$.main(ArtyA7SmpLinux.scala:453)
[error] saxon.board.digilent.ArtyA7SmpLinux.main(ArtyA7SmpLinux.scala)
[error] ********************************************************************************
[error] ********************************************************************************
[error] Assignment data type mismatch
[error] (toplevel/sdramDomain_phyA_logic_phy/??? : Bool) := (toplevel/sdramDomain_phyA_logic_phy/io_sdram_DQS : inout Bits[2 bits])
[error] saxon.board.digilent.ArtyA7SmpLinux$.main(ArtyA7SmpLinux.scala:453)
[error] saxon.board.digilent.ArtyA7SmpLinux.main(ArtyA7SmpLinux.scala)
[error] ********************************************************************************
[error] ********************************************************************************
[error] Assignment data type mismatch
[error] (toplevel/sdramDomain_phyA_logic_phy/??? : Bool) := (toplevel/sdramDomain_phyA_logic_phy/io_sdram_DQSn : inout Bits[2 bits])
[error] saxon.board.digilent.ArtyA7SmpLinux$.main(ArtyA7SmpLinux.scala:453)
[error] saxon.board.digilent.ArtyA7SmpLinux.main(ArtyA7SmpLinux.scala)
[error] ********************************************************************************
[error] ********************************************************************************
[error] Assignment data type mismatch
[error] (toplevel/sdramDomain_phyA_logic_phy/??? : Bool) := (toplevel/sdramDomain_phyA_logic_phy/io_sdram_DQSn : inout Bits[2 bits])
[error] saxon.board.digilent.ArtyA7SmpLinux$.main(ArtyA7SmpLinux.scala:453)
[error] saxon.board.digilent.ArtyA7SmpLinux.main(ArtyA7SmpLinux.scala)
[error] ********************************************************************************
[error] ********************************************************************************
[error] Design's errors are listed above.
[error] SpinalHDL compiler exit stack :
[error] at spinal.core.SpinalExit$.apply(Misc.scala:440)
[error] at spinal.core.SpinalError$.apply(Misc.scala:495)
[error] at spinal.core.internals.PhaseContext.checkPendingErrors(Phase.scala:174)
[error] at spinal.core.internals.PhaseContext.doPhase(Phase.scala:190)
[error] at spinal.core.internals.SpinalVerilogBoot$$anonfun$singleShot$2$$anonfun$apply$141.apply(Phase.scala:2746)
[error] at spinal.core.internals.SpinalVerilogBoot$$anonfun$singleShot$2$$anonfun$apply$141.apply(Phase.scala:2744)
[error] at scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59)
[error] at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48)
[error] at spinal.core.internals.SpinalVerilogBoot$$anonfun$singleShot$2.apply(Phase.scala:2744)
[error] at spinal.core.internals.SpinalVerilogBoot$$anonfun$singleShot$2.apply(Phase.scala:2680)
[error] at spinal.core.ScopeProperty$.sandbox(ScopeProperty.scala:69)
[error] at spinal.core.internals.SpinalVerilogBoot$.singleShot(Phase.scala:2680)
[error] at spinal.core.internals.SpinalVerilogBoot$.apply(Phase.scala:2675)
[error] at spinal.core.Spinal$.apply(Spinal.scala:405)
[error] at spinal.core.SpinalConfig.generateVerilog(Spinal.scala:173)
[error] at saxon.board.digilent.ArtyA7SmpLinux$.main(ArtyA7SmpLinux.scala:453)
[error] at saxon.board.digilent.ArtyA7SmpLinux.main(ArtyA7SmpLinux.scala)
[error] Nonzero exit code returned from runner: 1
[error] (Compile / runMain) Nonzero exit code returned from runner: 1
[error] Total time: 7 s, completed 2023-12-27 9:51:12

I followed the steps in README.
The running environment is Ubuntu 22.

Roadmap

  • SDRAM working in sim
  • Linux working in sim
  • Figuring out the exact linux memory mapping requirements
  • Having a common memory map between non cached and cached stuff
  • Defining basic cacheless and cache-full-linux-ready SoCs
  • Having hardware to run those two soc
  • Having a ice40 XIP SoC
  • Having Linux on ice40 8K
  • BMB decoder should protect slaves from access with burst length too long
  • Soc on UP5K
  • Bmb flow/Stream rsp
  • Linux boot loader
  • SDRAM-DDR support

I want to change cpu config in Ulx3SMinimal.scala,but got error.

Hi.

I have started to use SaxonSoC.
To change the CPU settings, I have changed the configuration part of Ulx3SMinimal.scala.

Like...

 //cpu.config.load(VexRiscvConfigs.minimal)
 cpu.config.load(VexRiscvConfigs.muraxLike)

I got the following error.

Why is this?
What should I do?

[error] Exception in thread "main" spinal.core.SpinalExit:
[error]  Error detected in phase PhaseCheck_noLatchNoOverride
[error] ********************************************************************************
[error] ********************************************************************************
[error] NO DRIVER ON (toplevel/system_cpu_logic_cpu/timerInterrupt : in Bool), defined at
[error]     vexriscv.plugin.CsrPlugin.setup(CsrPlugin.scala:590)
[error]     vexriscv.plugin.CsrPlugin.setup(CsrPlugin.scala:434)
[error]     vexriscv.Pipeline$$anonfun$build$2.apply(Pipeline.scala:47)
[error]     vexriscv.Pipeline$$anonfun$build$2.apply(Pipeline.scala:47)
[error]     vexriscv.Pipeline$class.build(Pipeline.scala:47)
[error]     vexriscv.VexRiscv.build(VexRiscv.scala:122)
[error]     vexriscv.Pipeline$$anonfun$1.apply$mcV$sp(Pipeline.scala:161)
[error]     vexriscv.VexRiscvBmbGenerator$$anonfun$7$$anon$2.<init>(VexRiscvBmbGenerator.scala:95)
[error]     vexriscv.VexRiscvBmbGenerator$$anonfun$7.apply(VexRiscvBmbGenerator.scala:90)
[error]     vexriscv.VexRiscvBmbGenerator$$anonfun$7.apply(VexRiscvBmbGenerator.scala:90)
[error]     spinal.sim.JvmThread.run(SimManager.scala:51)
[error] ********************************************************************************
[error] ********************************************************************************
[error] NO DRIVER ON (toplevel/system_cpu_logic_cpu/externalInterrupt : in Bool), defined at
[error]     vexriscv.plugin.CsrPlugin.setup(CsrPlugin.scala:591)
[error]     vexriscv.plugin.CsrPlugin.setup(CsrPlugin.scala:434)
[error]     vexriscv.Pipeline$$anonfun$build$2.apply(Pipeline.scala:47)
[error]     vexriscv.Pipeline$$anonfun$build$2.apply(Pipeline.scala:47)
[error]     vexriscv.Pipeline$class.build(Pipeline.scala:47)
[error]     vexriscv.VexRiscv.build(VexRiscv.scala:122)
[error]     vexriscv.Pipeline$$anonfun$1.apply$mcV$sp(Pipeline.scala:161)
[error]     vexriscv.VexRiscvBmbGenerator$$anonfun$7$$anon$2.<init>(VexRiscvBmbGenerator.scala:95)
[error]     vexriscv.VexRiscvBmbGenerator$$anonfun$7.apply(VexRiscvBmbGenerator.scala:90)
[error]     vexriscv.VexRiscvBmbGenerator$$anonfun$7.apply(VexRiscvBmbGenerator.scala:90)
[error]     spinal.sim.JvmThread.run(SimManager.scala:51)
[error] ********************************************************************************
[error] ********************************************************************************

SAXON_CPU_COUNT >4 woes

Hi,

Great update to the readme - thanks.

Out of curiosity, I've been playing with the latest version and wanted to find the max I can do with an 85k Ulx3s board.
Mainly I wanted to see how many hearts I can fit.
SAXON_CPU_COUNT=6 seems to work to create a bitstream with 6 cores (at least I think it does - in the build log I see references to the additional cores)

Linux is a different story.
I added two more cpu definition blocks to ./buildroot-spinal-saxon/boards/common/dts/linux_cpu.dts.

linux boots but reports cpu 4 and 5 as failed to start
[ 0.117618] smp: Bringing up secondary CPUs ...
[ 0.194216] CPU4: failed to start
[ 0.212434] CPU5: failed to start
[ 0.214449] smp: Brought up 1 node, 4 CPUs

unsure if ./buildroot-spinal-saxon/boards/common/dts/linux_plic_link.dts needs extending too. Please advise

Trying to digg a little deeper I found that u-boot only reports 4 cpus
=> cpu list
0: cpu@0 rv32ima
1: cpu@1 rv32ima
2: cpu@2 rv32ima
3: cpu@3 rv32ima

found uboot.dts and tried adding 2 more cpu definitions (./buildroot-spinal-saxon/boards/spinal-saxon/ulx3s/u-boot/uboot.dts)
but still only 4 cpus in linux and uboot

poking around some more, I found this uboot config file (in ./build/uboot-smp-latest/configs/saxon_bsp_defconfig) with the default of 4 cpus. Changing CONFIG_NR_CPUS from 4 to 6 doesn't seem to stick though. it is overwritten in every run of saxon_buildroot
Performing just saxon_buildroot_compile after the change prevents it from being overwritten but still doesn't solve the problem

Any idea what I'm missing?

Thanks

saxon smp linux in verilator - feature request

hi,

i am completely new to spinal hdl and vexriscv
and i have knowledge about verilog linux and buildroot
i compiled Linux.scala and simulated linux in verilator and i like it because it is fast.
i want to simulate dual core with simple uart and SMP linux in verilator

  • maybe this can be done with saxon soc or VexRiscvSmpCluster.scala
    but i am blocked with system interconnections
    i want it simple to be fast and easier to understand.
    i think this is an essential feature.

    can you put this feature on your agenda, please
    or give some detailed hints

thank you

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