riscv-mcu/e203_hbirdv2

The Ultra-Low Power RISC-V Core

RISCV MCU

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The riscv-mcu orginization in Github is to save RISC-V MCU relevant dococoments and projects. For the compherensive information please visit www.riscv-mcu.com

e203_hbirdv2's Issues

Docs for NICE interface

Thank you very much for sharing the revised version of E203. It is nice to have the NICE co-processor interface included in your code.

The problem now is how to write users' own co-processors/accelerators. Any Docs on the NICE interface? It will be best if examples can be included.

Regards,
Xing

Nuclei Studio 2022.08版本无法正常下载程序到hbird/hbirdv2 flash上

蜂鸟SoC使用OpenOCD 0.11.0+dev-02420-g1d0387cb版本，在ilm下载模式运行正确，在flash/flashxip下载模式会报错，可以连接上，下载时报错，截图如下。

跑仿真遇到的一些问题

我根据quickstart里面的指导进行仿真，遇到了以下的一些问题：

1.README存在一些小问题

/e203_hbirdv2/vsim/README.md中的第十四行:
原代码：make compile SIM=iverlog **or** make compile SIM=VCS
这里的的iverilog少了个i。

2.对于Ubuntu22.04需要进行额外配置

我进行到4.1.3. Run simulation tests时，执行make run_test SIM=iverilog命令时报错，报错信息：Syntax error: "&"unexpected。
我根据这个解决了问题。希望可以将这个问题加入文档中，让以后走到这一步的同学少走一些弯路。

Nuclei Studio IDE User guide for e203_hbirdv2 is not update to date 蜂鸟二代IDE使用文档对不上

根据文档所描述的 https://doc.nucleisys.com/hbirdv2/quick_start/ide.html 下载IDE，发现没法和最新的IDE匹配上请更新。

这里的文档能匹配的应该是 2020.09版本

最新的 2022.04版本无法正常使用，最新的版本使用的是NPK方式，请参照IDE文档。

蜂鸟v1/v2这里采用的hbird-sdk的NPK包，可以从https://github.com/riscv-mcu/hbird-sdk/releases/tag/0.1.3 这里下载zip包，然后通过Nuclei Package Management导入，然后使用Create Nuclei RISC-V C/C++ Project选择HummingBird对应的开发板和SoC创建对应的使用用例。

add new SRAM to e203

Hi,

as we know, there are 2 internal SRAM: ITCM and DTCM in e203.
my questions are:

1. how to change DTCM size?
2. I would like to add new SRAM IP to e203, is there any example about how to add it?

How to run an OS on e203_hbird?

Would you please publish a tutorial about how to run an OS on e203_hbird? Or please let me know where there is a such tutorial?

some question about E203

1. How to add burst transmission function to AXI protocol of E203
2. How to improve the continuous reading and writing rate of APB/AXI, now the continuous reading and writing is too slow, as shown in the following figure
   

Problem with Modelsim simulation

I found there are some minor bugs when build simulation using Modelsim:

(1) In the file e203_soc_top.v
`include "e203_defines.v" was omitted in the very begin,
which caused definitions of macros missing in the codes.

(2) In the file tb_top.v
line 270: $readmemh({testcase, ".verilog"}, itcm_mem);
Seems #0 would be added in the beginning:
#0 $readmemh({testcase, ".verilog"}, itcm_mem);
or there may exists race hazard with $value$plusargs statement.

关于PLIC部分代码是否可综合问题（Is the plic code synthesizable ？ ）

please ，Is the plic code synthesizable ？，Thanks！

question occurs when i run qsort example program on e203

subprogram can‘t return main function through ret instr. For example, verify_qsort funct can't return main, when executing 0x80001074 pc directly jumps to 0x00000000 ,then jumps to interrupt funct - trap_entry(0x80000120) ，as shown in the figure below。
。

According to my understanding，the right process is that verify_qsot returns to main , main returns to _init , _init returns to exit.
So , please tell me whether qsort program can run on e203 , or where does problem maybe occur ?

关于移植到xc7z100ffg9-2出现的问题

您好，我想请教一下，我现在把e203移植到另外一块开发板出现了以下的问题：
1、由于这块开发板的特殊性，上面的32.768KHz时钟不能供给PL端使用，所以vivado在综合的时候，这条时序路径会报错。这个问题该怎么解决？是可以忽略的吗？
2、移植过去之后，我把jtag接口和gpioA上的uart接口引了出来但是出现了以下报错：

为什么会没有检测到内核？

e203调试器选型

请问CMSIS，DapLink或者一般的Jlink可以用于调试吗？是否有对应的版本或者芯片型号的要求？

regression case rv32um-p-div fail

xrun -r sp_default +DUMPWAVE=1 +TESTCASE=/home/icer/work/test/e203_hbirdv2-master/vsim/run/../../riscv-tools/riscv-tests/isa/generated/rv32um-p-div +SIM_TOOL=xrun 2>&1 | tee rv32um-p-div/rv32um-p-div.log; cd /home/icer/work/test/e203_hbirdv2-master/vsim/run;
TOOL: xrun 20.09-s009: Started on Jan 27, 2024 at 21:16:47 CST
TOOL: xrun(64) 20.09-s009: Started on Jan 27, 2024 at 21:16:47 CST
xrun(64): 20.09-s009: (c) Copyright 1995-2021 Cadence Design Systems, Inc.
xrun: *N,NOSNPR: The default work directory (./xcelium.d/run.lnx8664.20.09.d) is missing. -r sp_default was used and a matching -snapshot sp_default scratch directory was found. xrun will imply the option -snapshot sp_default.
Loading snapshot worklib.sp_default:v .................... Done
SVSEED default: 1
xmsim: *W,RNDXCELON: A newer version of the SystemVerilog constraint solver is being used which has better support for array-solving, new solve-order mechanism, and seed stability enhancements..
xcelium> source /opt/rh/XCELIUM2009/tools/xcelium/files/xmsimrc
xcelium> run
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
TESTCASE= /home/icer/work/test/e203_hbirdv2-master/vsim/run/../../riscv-tools/riscv-tests/isa/generated/rv32um-p-div
xrun used
xmsim: *W,PRUASZ: Unpacked array at "tb_top.itcm_mem" of 65536 elements exceeds limit of 16384 - not probed
Use 'probe -create -unpacked 65536 tb_top.itcm_mem' or 'setenv SHM_UNPACKED_LIMIT 65536' to adjust limit.
ITCM 0x00: 340510730001aa0d
ITCM 0x01: ff85051300002517
ITCM 0x02: 01f5222301e52023
ITCM 0x03: 040f416334202f73
ITCM 0x04: 4fa507ff02634fa1
ITCM 0x05: 0c634fad05ff0f63
ITCM 0x06: 0bff05634f8505ff
ITCM 0x07: 4f9d0dff00634f95
ITCM 0x16: 2f03f52505130000
ITCM 0x20: 2f8300052f03f065
??????????????????????????????????????????
??????????????????????????????????????????
{i_mul,i_mulh,i_mulhsu,i_mulhu,i_div,i_divu,i_rem,i_remu}=00001000
muldiv_i_rs1=ffffffec
muldiv_i_rs2=00000006

golden_res=55555552
muldiv_o_wbck_wdat=fffffffd
??????????????????????????????????????????
xmsim: *F,ASRTST (../install/rtl/core/e203_exu_alu_muldiv.v,624): (time 93648 NS) Assertion tb_top.u_e203_soc_top.u_e203_subsys_top.u_e203_subsys_main.u_e203_cpu_top.u_e203_cpu.u_e203_core.u_e203_exu.u_e203_exu_alu.u_e203_exu_alu_muldiv.CHECK_GOLD_AND_ACTUAL_SAME has failed
Memory Usage - Current physical: 97.6M, Current virtual: 458.4M
CPU Usage - 0.6s system + 3.8s user = 4.3s total (100.0% cpu)
Simulation terminated via $fatal(2) at time 93648 NS + 6
../install/rtl/core/e203_exu_alu_muldiv.v:624 $fatal ("\n Error: Oops, This should never happen. \n");
xcelium> exit
TOOL: xrun(64) 20.09-s009: Exiting on Jan 27, 2024 at 21:16:50 CST (total: 00:00:03)
make[1]: Leaving directory `/home/icer/work/test/e203_hbirdv2-master/vsim/run'

artydevkit 支持

有没有计划增加 artydevkit支持，比如arty a7

Instructions can not be executed when using 16 general registers.

I try to use 16 general registers for the soc system, and modify the define "E203_CFG_REGNUM_IS_32" to "E203_CFG_REGNUM_IS_16" in config.v file.

But CPU just executed four instructions at the beginning of the firmware, and then hanged. It seems that exception happened.

Did some guys encounter this issue? Could you give me some suggestions?
Thanks!

apb_uart.v 文件中的fifo_tx_data信号问题

fifo_tx_data信号应该会被综合成latch吧（line#190行附近）。官方这样写何特殊用意？不是很理解，望解答。

求NICE接口搭载协处理器教程或者资源

我正在学习如何在NICE接口搭载协处理器，比如乘法器+加法器+……，然后用自定义指令1、2……去调用他们，请问大家有没有相关教程，或者相关资源，万分感谢！@、

[documentation] 4.1.2. Compile self-test cases

According to "4.1.2. Compile self-test cases" of the documentation i need to download prebuild Nuclei RISC-V GNU toolchain and extract bin directory to e203_hbirdv2/riscv-tools/prebuilt_tools/prefix/bin. I made this an tried to launch "source regen.sh", but the result was "riscv-nuclei-elf-gcc: fatal error: cannot execute 'cc1': execvp: No such file or directory".
I can find cc1 binary file in the downloaded archive in gcc/libexec/gcc/riscv-nuclei-elf/10.2.0, but i don't understand how to make it visible to riscv-nuclei-elf-gcc.