Topic: verilog Goto Github

👇 Here are 3907 public repositories matching this topic...

aappleby / metroboy
verilog,A repository of gate-level simulators and tools for the original Game Boy.
User: aappleby
verilog gameboy gameboy-emulator simulator emulator hdl

analogdevicesinc / hdl
verilog,HDL libraries and projects
Organization: analogdevicesinc
Home Page: https://wiki.analog.com/resources/fpga/docs/hdl
analog-devices hdl jesd204b verilog fpga hacktoberfest

chipsalliance / chisel
verilog,Chisel: A Modern Hardware Design Language
Organization: chipsalliance
Home Page: https://www.chisel-lang.org/
chisel chisel3 scala firrtl rtl chip-generator verilog

circuitvalley / usb_c_industrial_camera_fpga_usb3
verilog,Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.
User: circuitvalley
camera fpga usb usb3 verilog csi mipi mipi-csi-receiver uvc

clash-lang / clash-compiler
verilog,Haskell to VHDL/Verilog/SystemVerilog compiler
Organization: clash-lang
Home Page: https://clash-lang.org/
haskell hardware-description-language fpga vhdl verilog systemverilog asic

cocotb / cocotb
verilog,cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
Organization: cocotb
Home Page: https://www.cocotb.org
python vhdl verilog uvm verification test

darklife / darkriscv
verilog,opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Organization: darklife
riscv processor-design rv32i rv32e verilog risc-v fpga rtl softcore core

drom / awesome-hdl
verilog,Hardware Description Languages
User: drom
awesome awesome-list hardware-description-language verilog vhdl hdl hacktoberfest

fpgawars / apio
verilog,:seedling: Open source ecosystem for open FPGA boards
Organization: fpgawars
Home Page: https://github.com/FPGAwars/apio/wiki
apio cli icestorm fpga lattice verilog package manager python

fpgawars / icestudio
verilog,:snowflake: Visual editor for open FPGA boards
Organization: fpgawars
Home Page: https://icestudio.io
editor fpga blocks icestorm lattice verilog ide icestudio javascript

google / xls
verilog,XLS: Accelerated HW Synthesis
Organization: google
Home Page: http://google.github.io/xls/
compiler high-level-synthesis hls open-source pipeline verilog mid-level-synthesis

hughperkins / verigpu
verilog,OpenSource GPU, in Verilog, loosely based on RISC-V ISA
User: hughperkins
verilog risc-v risc-v-assembly hardware-designs asic-design gpu gpu-acceleration machine-learning verification

jbush001 / nyuziprocessor
verilog,GPGPU microprocessor architecture
User: jbush001
fpga gpu-computing gpu verilog hardware microprocessor graphics processor-architecture

leiwang1999 / fpga
verilog,帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目
User: leiwang1999
fpga xilinx verilog vivado pynq

logisim-evolution / logisim-evolution
verilog,Digital logic design tool and simulator
Organization: logisim-evolution
circuit circuits digital-circuit digital-circuits digital-logic digital-logic-design education fpga logic logisim logisim-evolution simulator timing-diagram verilog vhdl

lvyufeng / step_into_mips
verilog,一步一步写MIPS CPU
User: lvyufeng
mips-cpu nscscc verilog

mikepopoloski / slang
verilog,SystemVerilog compiler and language services
User: mikepopoloski
compiler language-service parse slang systemverilog verilog

obijuan / open-fpga-verilog-tutorial
verilog,Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
User: obijuan
verilog icestorm linux lattice fpgawars openfpga fpga

olofk / edalize
verilog,An abstraction library for interfacing EDA tools
User: olofk
eda fpga fossi xilinx altera lattice yosys synthesis simulation verilog

olofk / fusesoc
verilog,Package manager and build abstraction tool for FPGA/ASIC development
User: olofk
python eda reuse package-manager fpga verilog vhdl

olofk / serv
verilog,SERV - The SErial RISC-V CPU
User: olofk
verilog fpga asic risc-v

open-sdr / openwifi
verilog,open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
Organization: open-sdr
802-11 ad9361 analog-devices csma dma fpga hardware hls ieee80211 linux mac80211 ofdm openwifi sdr software-defined-radio verilog wifi xilinx xilinx-fpga zynq

open-sdr / openwifi-hw
verilog,open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
Organization: open-sdr
ad9361 analog-devices csma dma fpga hardware hls ieee80211 linux mac80211 ofdm rtl sdr software-defined-radio verilog vhdl wi-fi xilinx zynq

opentimer / opentimer
verilog,A High-performance Timing Analysis Tool for VLSI Systems
Organization: opentimer
static-timing-analysis sta vlsi vlsi-circuits vlsi-physical-design cpp17 parallel-computing circuit-simulator verilog electronic-design-automation

pconst / basic_verilog
verilog,Must-have verilog systemverilog modules
User: pconst
fpga delay debounce encoder xilinx altera verilog fifo tcl spi-master

platformio / platformio-vscode-ide
verilog,PlatformIO IDE for VSCode: The next generation integrated development environment for IoT
Organization: platformio
Home Page: https://marketplace.visualstudio.com/items?itemName=platformio.platformio-ide
platformio vscode iot debugger fpga microcontroller embedded verilog hardware

princetonuniversity / openpiton
verilog,The OpenPiton Platform
Organization: princetonuniversity
Home Page: http://www.openpiton.org
verilog python fpga processor research-platform

projf / projf-explore
verilog,Project F brings FPGAs to life with exciting open-source designs you can build on.
Organization: projf
Home Page: https://projectf.io
fpga graphics-hardware oshw verilog

redcrafter / verilog2factorio
verilog,This project will compile verilog (a hardware description language) into factorio blueprints.
User: redcrafter
Home Page: https://redcrafter.github.io/verilog2factorio/
verilog factorio compiler

rejunity / z80-open-silicon
verilog,Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.
User: rejunity
Home Page: https://rejunity.github.io/z80-open-silicon/
chip foss tinytapeout z80 cpu retrocomputing tapeout verilog

riscv-mcu / e203_hbirdv2
verilog,The Ultra-Low Power RISC-V Core
Organization: riscv-mcu
Home Page: https://doc.nucleisys.com/hbirdv2
risc-v riscv fpga hummingbird nuclei soc e203 china verilog low-power

seldridge / verilog
verilog,Repository for basic (and not so basic) Verilog blocks with high re-use potential
User: seldridge
verilog rtl hardware fpga

si-riscv / e200_opensource
verilog,Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
User: si-riscv
Home Page: https://github.com/riscv-mcu/e203_hbirdv2
risc-v ultra-low-power cpu core china verilog nuclei

spinalhdl / spinalhdl
verilog,Scala based HDL
Organization: spinalhdl
scala rtl vhdl verilog fpga

spinalhdl / vexriscv
verilog,A FPGA friendly 32 bit RISC-V CPU implementation
Organization: spinalhdl
riscv soc cpu spinalhdl vhdl verilog fpga softcore

splinedrive / kianriscv
verilog,RISC-V Linux SoC, marchID: 0x2b
User: splinedrive
riscv verilog fpga cpu linux bare-metal mmu rv32ima sv32 systemverilog

stnolting / neorv32
verilog,:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
User: stnolting
Home Page: https://neorv32.org
risc-v soft-core vhdl fpga soc microcontroller processor cpu riscv system-on-chip

sudhamshu091 / 32-verilog-mini-projects
verilog,Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM
User: sudhamshu091
verilog verilog-project miniproject verilog-hdl

syntacore / scr1
verilog,SCR1 is a high-quality open-source RISC-V MCU core in Verilog
Organization: syntacore
riscv risc-v rtl verilog rv32i rv32e rv32imc rv32emc ip core

terostechnology / vscode-teroshdl
verilog,VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
Organization: terostechnology
Home Page: https://terostechnology.github.io/terosHDLdoc/
verilog vhdl systemverilog fpga

the-openroad-project / openlane
verilog,OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Organization: the-openroad-project
Home Page: https://openlane.readthedocs.io/
asic 130nm magic netgen yosys openroad skywater openram vlsi system-on-chip

the-openroad-project / openroad
verilog,OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Organization: the-openroad-project
Home Page: https://theopenroadproject.org/
opendb-database openroad lef verilog timing-analysis def eda rtl gdsii cpp

ultraembedded / biriscv
verilog,32-bit Superscalar RISC-V CPU
User: ultraembedded
risc-v rv32i rv32im superscalar cpu fpga verilog pipelined-processors verilator coremark

ultraembedded / cores
verilog,Various HDL (Verilog) IP Cores
User: ultraembedded
verilog rtl verilog-hdl fpga verilator verilog-components asic sdram sram audio

ultraembedded / riscv
verilog,RISC-V CPU Core (RV32IM)
User: ultraembedded
risc-v cpu verilog fpga verilator rv32im rv32i riscv-linux pipeline-processor asic

verilator / verilator
verilog,Verilator open-source SystemVerilog simulator and lint system
Organization: verilator
Home Page: https://verilator.org
compilers cpp rtl system-verilog systemc verilator verilog verilog-simulator

verilog-to-routing / vtr-verilog-to-routing
verilog,Verilog to Routing -- Open Source CAD Flow for FPGA Research
Organization: verilog-to-routing
Home Page: https://verilogtorouting.org
cad eda fpga placement routing synthesis verilog vpr vtr

wangxuan95 / fpga-usb-device
verilog,An FPGA-based USB full-speed device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB full-speed device端控制器，可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备，只需要3个FPGA普通IO，而不需要额外的接口芯片。
User: wangxuan95
Home Page: https://gitee.com/wangxuan95/FPGA-USB-Device
fpga verilog rtl usb usb-cdc usb-serial usb-uart usb-hid usb-keyboard usb-device

xiaop1 / verilog-practice
verilog,HDLBits website practices & solutions
User: xiaop1
hdlbits practice verilog

zipcpu / zipcpu
verilog,A small, light weight, RISC CPU soft core
User: zipcpu
fpga soft-core cross-compiler verilog verilator wishbone wishbone-bus zipcpu cpu risc-cpu