ultraembedded/cores

Various HDL (Verilog) IP Cores

Various HDL (Verilog) IP Cores

Github: http://github.com/ultraembedded/cores

Cloning

This repo contains submodules, to clone them;

git clone --recursive https://github.com/ultraembedded/cores.git

Catalogue

Name	Description
asram16_axi4	AXI4 -> Async SRAM (16-bit) Interface
dbg_bridge	UART -> AXI4 Debug Bridge
dvi_framebuffer	DVI/HDMI framebuffer with AXI-4 bus master
ftdi_async_bridge	FTDI Asynchronous FIFO Interface (Wishbone)
ftdi_bridge	FTDI Asynchronous/Synchronous FIFO Interface (AXI-4)
ft60x_axi	FTDI FT601 USB3.0 to high-performance AXI4 bus master
i2s	I2S Master
irq_ctrl	Simple Linux support interrupt controller
sdram	Simple SDRAM Controller (Wishbone)
sdram_axi4	Simple SDRAM Controller (AXI-4)
spdif	SPDIF Transmitter
spiflash	SPI-Flash XIP Interface
spilite_axi4l	SPI-Lite SPI Master Interface
uart	UART
ulpi_wrapper	ULPI Link Wrapper
usb_bridge	USB -> AXI4-Lite Debug Bridge
usb_cdc	USB CDC Device
usb_device	USB Peripheral Interface
usb_fs_phy	USB Full Speed PHY
usb_host	USB 1.1 Host Controller
usb_sniffer	USB Sniffer
usb_serial	USB to UART

cores's Issues

uart/testbench does not work

For me uart_cfg_div does not get set:

Moreover above vardump diverges from what $display outputs:

rst_i = 0, write_en_w = 0, addr_i =   0, data_i =  15
rst_i = 0, write_en_w = 1, addr_i =   0, data_i =   0

In last output write_en_w becomes 1 only after data_i is already zero.

How can it be possible?

666

I am a digital IC designer,i like your proj

wrap_detect_q is never set on for one-shot sniffing

For wrap_detect_q to be one we need buffer_wr_q on when write_addr_q == buffer_end_w. But since write_addr_q == buffer_end_w we get buffer_full_w and it moves us to STATE_RX_DATA_IGNORE and we will never get write_addr_q.

Issue in ulpi_wrapper

I believe there is a bug in this core. If a register write is interrupted by an RX CMD update, the state machine will wait forever in the STATE_REG until the ulpi_nxt_i is asserted. At least this is what I'm observing in hardware when interfacing with an SMSC USB3300 chip. The first register write (to Function Control) goes well but the second register write (to OTG Control) is interrupted by an RX CMD and the ulpi_wrapper remains stuck in state 3.

Sdram_axi ip

Hi,
I want to know if the sdram_axi controller IP verified and tested ?
Can I get a document specifying each detail of it