ultraembedded/biriscv

32-bit Superscalar RISC-V CPU

biRISC-V - 32-bit dual issue RISC-V CPU

Github: http://github.com/ultraembedded/biriscv

Features

• 32-bit RISC-V ISA CPU core.
• Superscalar (dual-issue) in-order 6 or 7 stage pipeline.
• Support RISC-V’s integer (I), multiplication and division (M), and CSR instructions (Z) extensions (RV32IMZicsr).
• Branch prediction (bimodel/gshare) with configurable depth branch target buffer (BTB) and return address stack (RAS).
• 64-bit instruction fetch, 32-bit data access.
• 2 x integer ALU (arithmetic, shifters and branch units).
• 1 x load store unit, 1 x out-of-pipeline divider.
• Issue and complete up to 2 independent instructions per cycle.
• Supports user, supervisor and machine mode privilege levels.
• Basic MMU support - capable of booting Linux with atomics (RV-A) SW emulation.
• Implements base ISA spec v2.1 and privileged ISA spec v1.11.
• Verified using Google's RISCV-DV random instruction sequences using cosimulation against C++ ISA model.
• Support for instruction / data cache, AXI bus interfaces or tightly coupled memories.
• Configurable number of pipeline stages, result forwarding options, and branch prediction resources.
• Synthesizable Verilog 2001, Verilator and FPGA friendly.
• Coremark: 4.1 CoreMark/MHz
• Dhrystone: 1.9 DMIPS/MHz ('legal compile options' / 337 instructions per iteration)

A sequence showing execution of 2 instructions per cycle;

Documentation

• Configuration
• Booting Linux
• Integration
• Custom Features

Similar Cores

• SiFive E76
  • RV32IMAFC
  • Dual issue in-order 8 stage pipeline
  • 4 ALU units (2 early, 2 late)
  • ✖️ Commercial closed source core/$$
• WD SweRV RISC-V Core EH1
  • RV32IMC
  • Dual issue in-order 9 stage pipeline
  • 4 ALU units (2 early, 2 late)
  • ✖️ System Verilog + auto signal hookup
  • ✖️ No data cache option
  • ✖️ Not able to boot Linux

Project Aims

• Boot Linux all the way to a functional userspace environment. ✔️
• Achieve competitive performance for this class of in-order machine (i.e. aim for 80% of WD SweRV CoreMark score). ✔️
• Reasonable PPA / FPGA resource friendly. ✔️
• Fit easily onto cheap hobbyist FPGAs (e.g. Xilinx Artix 7) without using all LUT resources and synthesize > 50MHz. ✔️
• Support various cache and TCM options. ✔️
• Be constructed using readable, maintainable and documented IEEE 1364-2001 Verilog. ✔️
• Simulate in open-source tools such as Verilator and Icarus Verilog. ✔️
• In later releases, add support for atomic extensions.

Booting the stock Linux 5.0.0-rc8 kernel built for RV32IMA to userspace on a Digilent Arty Artix 7 with biRISC-V (with atomic instructions emulated in the bootloader);

Prior Work

Based on my previous work;

• Github: http://github.com/ultraembedded/riscv

Getting Started

Cloning

To clone this project and its dependencies;

git clone --recursive https://github.com/ultraembedded/biriscv.git

Running Helloworld

To run a simple test image on the core RTL using Icarus Verilog;

# Install Icarus Verilog (Debian / Ubuntu / Linux Mint)
sudo apt-get install iverilog

# [or] Install Icarus Verilog (Redhat / Centos)
#sudo yum install iverilog

# Run a simple test image (test.elf)
cd tb/tb_core_icarus
make

The expected output is;

Starting bench
VCD info: dumpfile waveform.vcd opened for output.

Test:
1. Initialised data
2. Multiply
3. Divide
4. Shift left
5. Shift right
6. Shift right arithmetic
7. Signed comparision
8. Word access
9. Byte access
10. Comparision

Configuration

Param Name	Valid Range	Description
SUPPORT_SUPER	1/0	Enable supervisor / user privilege levels.
SUPPORT_MMU	1/0	Enable basic memory management unit.
SUPPORT_MULDIV	1/0	Enable HW multiply / divide (RV-M).
SUPPORT_DUAL_ISSUE	1/0	Support superscalar operation.
SUPPORT_LOAD_BYPASS	1/0	Support load result bypass paths.
SUPPORT_MUL_BYPASS	1/0	Support multiply result bypass paths.
SUPPORT_REGFILE_XILINX	1/0	Support Xilinx optimised register file.
SUPPORT_BRANCH_PREDICTION	1/0	Enable branch prediction structures.
NUM_BTB_ENTRIES	2 -	Number of branch target buffer entries.
NUM_BTB_ENTRIES_W	1 -	Set to log2(NUM_BTB_ENTRIES).
NUM_BHT_ENTRIES	2 -	Number of branch history table entries.
NUM_BHT_ENTRIES_W	1 -	Set to log2(NUM_BHT_ENTRIES_W).
BHT_ENABLE	1/0	Enable branch history table based prediction.
GSHARE_ENABLE	1/0	Enable GSHARE branch prediction algorithm.
RAS_ENABLE	1/0	Enable return address stack prediction.
NUM_RAS_ENTRIES	2 -	Number of return stack addresses supported.
NUM_RAS_ENTRIES_W	1 -	Set to log2(NUM_RAS_ENTRIES_W).
EXTRA_DECODE_STAGE	1/0	Extra decode pipe stage for improved timing.
MEM_CACHE_ADDR_MIN	32'h0 - 32'hffffffff	Lowest cacheable memory address.
MEM_CACHE_ADDR_MAX	32'h0 - 32'hffffffff	Highest cacheable memory address.

biriscv's Issues

Benchmark scores

To run dhrystone and coremark, it needs to exceed 64Kb. I modified the code with 128Kb TCM in the following path, and added env to run it.

https://github.com/kuopinghsu/biriscv

I got the following benchmark scores,

Coremark:
In memory: CoreMark/MHz: 3.333047
In TCM: CoreMark/MHz: 3.345606

Benchmark:
In memory: DMIPS_Per_MHz: 2.243
In TCM: DMIPS_Per_MHz: 2.415

I can't get a score of 4.1 CoreMark/MHz mentioned by the biRISC-V core. Could you share how to get 4.1 CoreMark/MHz score?

undefined reference to `VlThreadPool::VlThreadPool(VerilatedContext*, unsigned int)'

I have this error when running makefile in tb/tb_top.
May I ask what version of verilator do you use?
I use v5.012

./lib/libsyscverilated.a: undefined reference to VlThreadPool::VlThreadPool(VerilatedContext*, unsigned int)' collect2: error: ld returned 1 exit status make[1]: *** [build/test.x] Error 1 make[1]: Leaving directory /disk2/others/dsd_311591023/try/biriscv/tb/tb_top'
make: *** [build] Error 2

Questions Biriscv

Dear,
I have a questions over Biriscv, is it possible contact a mail.
Sincerely
Emilio

TCL file for FPGA build

Hello,

You have done great work!
Could you please share with us the TCL script used/generated from the FPGA run?
And maybe more details on building the image and FPGA run flow?

Thanks a lot,
Alaa

Using own ELF results in an infinite loop

So as the title suggests, I am trying to simulate the CPU with my own ELF files. When doing so the simulator hangs in an infinite loop. I used riscv32-unknown-elf-gcc to compile the *.c code with no other flags or arguments. I've also tried using the example provided but it had the same result. Any ideas why that is?

Wrong opcode for CSR_MCYCLE, CSR_MTIME and CSR_MTIMEH

According to the "ricv_privileged_spec" document on page 8 the instructions 0xC00, 0xC01 and 0xC80 refer to user-side instructions, while the machine-side instructions, i.e. mcycle, mtime and mcycleh are described on page 11 with the following opcodes: 0xB00, 0XB01, 0xB80.

In biriscv_defs on line 350 there are definitions to be modified.

DEBUG interface

Hi,

Do you have plan to design the DEBUG interface?

Linux compatibility

Hello,
Does this core be able to run Linux on it.

about Branch target buffer

I notice that your branch target buffer is a Register file, which have no read latency. So I got two question:

Is this a usual way to use Register file as BTB rather than use a block of sram?
And if we use sram, comparing to register file, there may be one cycle delay for read operation. I think the read delay disturb the design of branch prediction. How to handle it?

Best regards

Consider adding biriscv to LiteX CPU ecosystem?

I would be super interested in seeing the biriscv be added to the LiteX CPU ecosystem so it could be easily compared to other options like VexRISCV / Rocket / etc. It would be easy to compare via https://antmicro.github.io/embench-tester/ (https://github.com/antmicro/embench-tester).

It would also be awesome to have another 32bit RISC-V option for https://github.com/litex-hub/linux-on-litex-vexriscv

There is some information at https://github.com/enjoy-digital/litex/wiki/Add-A-New-CPU and https://github.com/enjoy-digital/litex/wiki/CPUs

Division by 0

Is it true that the processor does not handle exceptions for division by zero, and will return FFFFFFFF every time?

Boot RISC-V Linux Failed, ERROR: Invalid opcode: 30529073 at PC: 8040016c

I assembly riscv-gnu-toolchain, riscv-linux-boot, riscv-linux-prebuilt and biriscv in one path, and run script such as:

#!/bin/sh

set -ex

RISCV_ROOT=`pwd`/riscv
if [ -d $RISCV_ROOT/tools ]; then
	echo $RISCV_ROOT/tools
else
	cd $RISCV_ROOT/riscv-gnu-toolchain
	git clean -fx -d
	git checkout .
	./configure --prefix=$RISCV_ROOT/tools --with-arch=rv32imzicsr
	make -j12
fi

export PATH=$PATH:$RISCV_ROOT/tools/bin

cd $RISCV_ROOT/riscv-linux-boot
make LINUX_DIR=../riscv-linux-prebuilt VMLINUX=../riscv-linux-prebuilt/kernel/vmlinux-rv32ima-5.0 DTS_FILE=../riscv-linux-prebuilt/dts/config32.dts

cd $RISCV_ROOT/biriscv/tb/tb_core_icarus
make clean
ELF_FILE=/home/uuz/riscv/riscv-linux-boot/riscv-linux-boot.elf make VERBOSE=1 run

vvp output the "RISC-V Linux Boot" LOGO:
| __ \|_ _|/ ____|/ ____| \ \ / / | | (_) | _ \ | | | |__) | | | | (___ | | _____\ \ / / | | _ _ __ _ ___ __ | |_) | ___ ___ | |_ | _ / | | \___ \| | |______\ \/ / | | | | '_ \| | | \ \/ / | _ < / _ \ / _ \| __| | | \ \ _| |_ ____) | |____ \ / | |____| | | | | |_| |> < | |_) | (_) | (_) | |_ |_| \_\_____|_____/ \_____| \/ |______|_|_| |_|\__,_/_/\_\ |____/ \___/ \___/ \__|
And then, report the error message:
ERROR: Invalid opcode: 30529073
at PC: 8040016c
ASSERT: ASSERT !"error" :0x109
How to solve this problem? Thanks everyone.

LWGP

Is LWGP supported by BIRISCV?

BIRISCV core is throwing the exception “0x02: Illegal Instruction” when it executes compiler/assembler generated instructions with GP suffix.

Here is firmware log where it detected the 0x02 exception:

In this case, when program counter reaches to the instruction ‘lwgp’:

The core raises the 0x02 exception:

It is to be noted that, the startup assembly file and the Makefile are configured correctly to define __global_pointer.

The following flag disables the GP usage, but results in worse code density:

Your advise is appreciated, thanks

How to use my own test programs?

What linker_script/compiler options should I use for my own C programs? Thanks!

make failed...error

'makefile:8: *** riscv32-unknown-elf-objcopy missing from PATH. Stop.'

Hello, an error occurred while trying to run the simulation as follows.
How can I solve the above error?

link library for biriscv

i am a student and currently working on a project related to biriscv and i require link library for the same from where ill get it from ??

Not an issue, rather a request

Hi,

Thanks a lot for sharing your work.
Will it be possible for you to share synthesis constraints files ?

Thanks and best regards
Bhawandeep Singh

How initializa the memory from the verilog

Dear,
I have a questions over Biriscv, is it possible contact a mail.
How to initialize the memory from the verilog file? Which are the steps to follow?
Sincerely
Emilio

Bug: Core should fault on misaligned branch source instruction, not on the target.

In v2.1 of the base ISA spec;

"An instruction-address-misaligned exception is generated on a taken branch or unconditional jump
if the target address is not four-byte aligned. This exception is reported on the branch or jump
instruction, not on the target instruction."

Operating Frequency

Hi All,
May i know the operating frequency of biriscv core.

Regards
Anand

Consider taping out core on SKY130 open source process with no cost shuttle program?

Do you think the biriscv would fit in the 10mm2 you get as part of the Google SkyWater MPW program? https://efabless.com/open_shuttle_program

@tdene has been working on a spreadsheet as part of this https://github.com/tdene/synth_opt_adders that shows the speed of adders that are possible.

FPGA Implementation

Any idea whether I can implement the following project on a PYNQ Z2 (ZYNQ XC7Z020-1CLG400C SoC) and what changes I should make to get linux booting on the PYNQ?

Bug: 'csr_swap' type operations on SATP register do not work

Issue:
Reading and writing (i.e. csr_swap) the CSR SATP register in the same operation will result in a 0 being returned regardless of the current SATP register contents.
Normally just writing the register, or just reading the register is fine.

This occurs due to the pipeline flush caused by this event which assumes it can squash the writeback result.

This is a fairly low priority issue as RISC-V Linux port does not try to do this operation.

JTAG Debugging Request

Hi,

I'm interested in the ARM Cortex-M alternatives, also bare metal, without Linux. (I'm currently using VexRiscv.)
I would like to check this core - or the single issue pipeline one - but I need the debugger interface for software development.
It would be a great if you could add it!

This is a relative good readable one:
https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_debug_dm.vhd
https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_debug_dtm.vhd

have a nice day,
nvitya