ultraembedded/biriscv

32-bit Superscalar RISC-V CPU

biriscv's Issues

Benchmark scores

To run dhrystone and coremark, it needs to exceed 64Kb. I modified the code with 128Kb TCM in the following path, and added env to run it.

https://github.com/kuopinghsu/biriscv

I got the following benchmark scores,

Coremark:
In memory: CoreMark/MHz: 3.333047
In TCM: CoreMark/MHz: 3.345606

Benchmark:
In memory: DMIPS_Per_MHz: 2.243
In TCM: DMIPS_Per_MHz: 2.415

I can't get a score of 4.1 CoreMark/MHz mentioned by the biRISC-V core. Could you share how to get 4.1 CoreMark/MHz score?

Operating Frequency

Hi All,
May i know the operating frequency of biriscv core.

Regards
Anand

Consider taping out core on SKY130 open source process with no cost shuttle program?

Do you think the biriscv would fit in the 10mm2 you get as part of the Google SkyWater MPW program? https://efabless.com/open_shuttle_program

@tdene has been working on a spreadsheet as part of this https://github.com/tdene/synth_opt_adders that shows the speed of adders that are possible.

Not an issue, rather a request

Hi,

Thanks a lot for sharing your work.
Will it be possible for you to share synthesis constraints files ?

Thanks and best regards
Bhawandeep Singh

Bug: Core should fault on misaligned branch source instruction, not on the target.

In v2.1 of the base ISA spec;

"An instruction-address-misaligned exception is generated on a taken branch or unconditional jump
if the target address is not four-byte aligned. This exception is reported on the branch or jump
instruction, not on the target instruction."

Wrong opcode for CSR_MCYCLE, CSR_MTIME and CSR_MTIMEH

According to the "ricv_privileged_spec" document on page 8 the instructions 0xC00, 0xC01 and 0xC80 refer to user-side instructions, while the machine-side instructions, i.e. mcycle, mtime and mcycleh are described on page 11 with the following opcodes: 0xB00, 0XB01, 0xB80.

In biriscv_defs on line 350 there are definitions to be modified.

How initializa the memory from the verilog

Dear,
I have a questions over Biriscv, is it possible contact a mail.
How to initialize the memory from the verilog file? Which are the steps to follow?
Sincerely
Emilio

about Branch target buffer

I notice that your branch target buffer is a Register file, which have no read latency. So I got two question:

Is this a usual way to use Register file as BTB rather than use a block of sram?
And if we use sram, comparing to register file, there may be one cycle delay for read operation. I think the read delay disturb the design of branch prediction. How to handle it?

Best regards

Questions Biriscv

Dear,
I have a questions over Biriscv, is it possible contact a mail.
Sincerely
Emilio

Bug: 'csr_swap' type operations on SATP register do not work

Issue:
Reading and writing (i.e. csr_swap) the CSR SATP register in the same operation will result in a 0 being returned regardless of the current SATP register contents.
Normally just writing the register, or just reading the register is fine.

This occurs due to the pipeline flush caused by this event which assumes it can squash the writeback result.

This is a fairly low priority issue as RISC-V Linux port does not try to do this operation.

Using own ELF results in an infinite loop

So as the title suggests, I am trying to simulate the CPU with my own ELF files. When doing so the simulator hangs in an infinite loop. I used riscv32-unknown-elf-gcc to compile the *.c code with no other flags or arguments. I've also tried using the example provided but it had the same result. Any ideas why that is?

link library for biriscv

i am a student and currently working on a project related to biriscv and i require link library for the same from where ill get it from ??

undefined reference to `VlThreadPool::VlThreadPool(VerilatedContext*, unsigned int)'

I have this error when running makefile in tb/tb_top.
May I ask what version of verilator do you use?
I use v5.012

./lib/libsyscverilated.a: undefined reference to VlThreadPool::VlThreadPool(VerilatedContext*, unsigned int)' collect2: error: ld returned 1 exit status make[1]: *** [build/test.x] Error 1 make[1]: Leaving directory /disk2/others/dsd_311591023/try/biriscv/tb/tb_top'
make: *** [build] Error 2

DEBUG interface

Hi,

Do you have plan to design the DEBUG interface?

JTAG Debugging Request

Hi,

I'm interested in the ARM Cortex-M alternatives, also bare metal, without Linux. (I'm currently using VexRiscv.)
I would like to check this core - or the single issue pipeline one - but I need the debugger interface for software development.
It would be a great if you could add it!

This is a relative good readable one:
https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_debug_dm.vhd
https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_debug_dtm.vhd

have a nice day,
nvitya

LWGP

Is LWGP supported by BIRISCV?

BIRISCV core is throwing the exception “0x02: Illegal Instruction” when it executes compiler/assembler generated instructions with GP suffix.

Here is firmware log where it detected the 0x02 exception:

In this case, when program counter reaches to the instruction ‘lwgp’:

The core raises the 0x02 exception:

It is to be noted that, the startup assembly file and the Makefile are configured correctly to define __global_pointer.

The following flag disables the GP usage, but results in worse code density:

Your advise is appreciated, thanks

Division by 0

Is it true that the processor does not handle exceptions for division by zero, and will return FFFFFFFF every time?

How to use my own test programs?

What linker_script/compiler options should I use for my own C programs? Thanks!

TCL file for FPGA build

Hello,

You have done great work!
Could you please share with us the TCL script used/generated from the FPGA run?
And maybe more details on building the image and FPGA run flow?

Thanks a lot,
Alaa

Boot RISC-V Linux Failed, ERROR: Invalid opcode: 30529073 at PC: 8040016c

I assembly riscv-gnu-toolchain, riscv-linux-boot, riscv-linux-prebuilt and biriscv in one path, and run script such as:

#!/bin/sh

set -ex

RISCV_ROOT=`pwd`/riscv
if [ -d $RISCV_ROOT/tools ]; then
	echo $RISCV_ROOT/tools
else
	cd $RISCV_ROOT/riscv-gnu-toolchain
	git clean -fx -d
	git checkout .
	./configure --prefix=$RISCV_ROOT/tools --with-arch=rv32imzicsr
	make -j12
fi

export PATH=$PATH:$RISCV_ROOT/tools/bin

cd $RISCV_ROOT/riscv-linux-boot
make LINUX_DIR=../riscv-linux-prebuilt VMLINUX=../riscv-linux-prebuilt/kernel/vmlinux-rv32ima-5.0 DTS_FILE=../riscv-linux-prebuilt/dts/config32.dts

cd $RISCV_ROOT/biriscv/tb/tb_core_icarus
make clean
ELF_FILE=/home/uuz/riscv/riscv-linux-boot/riscv-linux-boot.elf make VERBOSE=1 run

vvp output the "RISC-V Linux Boot" LOGO:
| __ \|_ _|/ ____|/ ____| \ \ / / | | (_) | _ \ | | | |__) | | | | (___ | | _____\ \ / / | | _ _ __ _ ___ __ | |_) | ___ ___ | |_ | _ / | | \___ \| | |______\ \/ / | | | | '_ \| | | \ \/ / | _ < / _ \ / _ \| __| | | \ \ _| |_ ____) | |____ \ / | |____| | | | | |_| |> < | |_) | (_) | (_) | |_ |_| \_\_____|_____/ \_____| \/ |______|_|_| |_|\__,_/_/\_\ |____/ \___/ \___/ \__|
And then, report the error message:
ERROR: Invalid opcode: 30529073
at PC: 8040016c
ASSERT: ASSERT !"error" :0x109
How to solve this problem? Thanks everyone.

make failed...error

'makefile:8: *** riscv32-unknown-elf-objcopy missing from PATH. Stop.'

Hello, an error occurred while trying to run the simulation as follows.
How can I solve the above error?

FPGA Implementation

Any idea whether I can implement the following project on a PYNQ Z2 (ZYNQ XC7Z020-1CLG400C SoC) and what changes I should make to get linux booting on the PYNQ?

Consider adding biriscv to LiteX CPU ecosystem?

I would be super interested in seeing the biriscv be added to the LiteX CPU ecosystem so it could be easily compared to other options like VexRISCV / Rocket / etc. It would be easy to compare via https://antmicro.github.io/embench-tester/ (https://github.com/antmicro/embench-tester).

It would also be awesome to have another 32bit RISC-V option for https://github.com/litex-hub/linux-on-litex-vexriscv

There is some information at https://github.com/enjoy-digital/litex/wiki/Add-A-New-CPU and https://github.com/enjoy-digital/litex/wiki/CPUs

Linux compatibility

Hello,
Does this core be able to run Linux on it.