olofk/serv

SERV - The SErial RISC-V CPU

SERV

SERV is an award-winning bit-serial RISC-V core

In fact, the award-winning SERV is the world's smallest RISC-V CPU. It's the perfect companion whenever you need a bit of computation and silicon real estate is at a premium.

How small is it then? Synthesizing the latest version of SERV in its most minimal form, yields the following results for some popular FPGA architectures and a typical CMOS process.

Lattice iCE40	Intel Cyclone 10LP	AMD Artix-7	CMOS
198 LUT	239 LUT	125 LUT	2.1kGE
164 FF	164 FF	164 FF

If you want to know more about SERV, what a bit-serial CPU is and what it's good for, I recommend starting out by watching the fantastic short SERV movies

• introduction to SERV
• SERV : RISC-V for a fistful of gates
• SERV: 32-bit is the New 8-bit
• Bit by bit - How to fit 8 RISC V cores in a $38 FPGA board (presentation from the Zürich 2019 RISC-V workshop)

All SERV videos and more can also be found here.

Apart from being the world's smallest RISC-V CPU, SERV also aims at being the best documented RISC-V CPU. For this there is an official SERV user manual with block diagrams that are correct to the gate-level, cycle-accurate timing diagrams and an in-depth description of how things work.

Systems using SERV

SERV can be easily integrated into any design, but if you are looking at just quickly trying it out, here is a list of some systems that are already using SERV:

Servant is the reference platform for SERV. It is a very basic SoC that contains just enough runs Zephyr RTOS. Servant is intended for FPGAs and has been ported to around 20 different FPGA boards. It is also used to run the RISC-V regression test suite.

CoreScore is an award-giving benchmark for FPGAs and their synthesis/P&R tools. It tests how many SERV cores that can be put into a particular FPGA.

Observer is a configurable and software-programmable sensor aggregation platform for heterogeneous sensors.

Subservient is a small technology-independent SERV-based SoC intended for ASIC implementations together with a single-port SRAM.

Litex is a Python-based framework for creating FPGA SoCs. SERV is one of the 30+ supported cores. A Litex-generated SoC has been used to run DooM on SERV.

Getting started

⭕ Create a root directory to keep all the different parts of the project together. We will refer to this directory as $WORKSPACE from now on.

$ export WORKSPACE=$(pwd)

All the following commands will be run from this directory unless otherwise stated.

• Install FuseSoC

    $ pip install fusesoc
  

• Add the FuseSoC standard library

    $ fusesoc library add fusesoc_cores https://github.com/fusesoc/fusesoc-cores
  

• The FuseSoC standard library already contain a version of SERV, but if we want to make changes to SERV, run the bundled example or use the Zephyr support, it is better to add SERV as a separate library into the workspace

    $ fusesoc library add serv https://github.com/olofk/serv
  

  ⚠️ The SERV repo will now be available in $WORKSPACE/fusesoc_libraries/serv. We will refer to that directory as $SERV.

• Install latest version of Verilator

• (Optional) To support RISC-V M-extension extension, Multiplication and Division unit (MDU) can be added included into the SERV as a separate library.

    $ fusesoc library add mdu https://github.com/zeeshanrafique23/mdu
  

  MDU will be available in $WORKSPACE/fusesoc_libraries/mdu

We are now ready to do our first exercises with SERV. If everything above is done correctly,we can use Verilator as a linter to check the SERV source code.

$ fusesoc run --target=lint serv

If everything worked, the output should look like

INFO: Preparing ::serv:1.2.1
INFO: Setting up project

INFO: Building simulation model
INFO: Running

After performing all the steps that are mentioned above, the directory structure from the $WORKSPACE should look like this:

.
$WORKSPACE
|
├── build
│   └── ...
├── fusesoc.conf
└── fusesoc_libraries
    ├── fusesoc_cores
    │   └── ...
    ├── mdu
    │   └── ...
    └── serv
        └── ...

Running pre-built test software

Build and run the single threaded zephyr hello world example with verilator (should be stopped with Ctrl-C):

fusesoc run --target=verilator_tb servant --uart_baudrate=57600 --firmware=$SERV/sw/zephyr_hello.hex

..or... the multithreaded version

fusesoc run --target=verilator_tb servant --uart_baudrate=57600 --firmware=$SERV/sw/zephyr_hello_mt.hex --memsize=16384

Both should yield an output ending with

***** Booting Zephyr OS zephyr-v1.14.1-4-gc7c2d62513fe *****
Hello World! service

For a more advanced example, we can also run the Dining philosophers demo

fusesoc run --target=verilator_tb servant --uart_baudrate=57600 --firmware=$SERV/sw/zephyr_phil.hex --memsize=32768

...or... the synchronization example

fusesoc run --target=verilator_tb servant --uart_baudrate=57600 --firmware=$SERV/sw/zephyr_sync.hex --memsize=16384

...or... the blinky example (note that the uart_baudrate should not be defined for the blinky test)

fusesoc run --target=verilator_tb servant --firmware=$SERV/sw/blinky.hex --memsize=16384

If the toolchain is installed, other applications can be tested by compiling the assembly program and converting to bin and then hex with makehex.py found in $SERV/sw.

💡RISC-V Compressed Extension can be enabled by passing --compressed=1 parameter.

Verification

SERV is verified using RISC-V compliance tests for the base ISA (RV32I) and the implemented extensions (M, C, Zicsr). The instructions on running Compliance tests using RISCOF framework are given in verif directory.

Other targets

The above targets are run on the servant SoC, but there are some targets defined for the CPU itself. Verilator can be run in lint mode to check for design problems by running

fusesoc run --target=lint serv

It's also possible to just synthesise for different targets to check resource usage and such. To do that for the iCE40 devices, run

fusesoc run --tool=icestorm serv --pnr=none

...or to synthesize with vivado for Xilinx targets, run

fusesoc run --tool=vivado serv --pnr=none

This will synthesize for the default Vivado part. To synthesise for a specific device, run e.g.

fusesoc run --tool=vivado serv --pnr=none --part=xc7a100tcsg324-1

Zephyr support

SERV, or rather the Servant SoC, can run the Zephyr RTOS. The Servant-specific drivers and BSP is located in the zephyr subdirectory of the SERV repository. In order to use Zephyr on Servant, a project directory structure must be set up that allows Zephyr to load the Servant-specific files as a module.

First, the Zephyr SDK and the "west" build too must be installed. The Zephyr getting started guide describes these steps in more detail.

Assuming that SERV was installed into $WORKSPACE/fusesoc_libraries/serv as per the prerequisites, run the following command to make the workspace also work as a Zephyr workspace.

west init

Specify the SERV repository as the manifest repository, meaning it will be the main entry point when Zephyr is looking for modules.

west config manifest.path $SERV

Get the right versions of all Zephyr submodules

west update

It should now be possible to build Zephyr applications for the Servant SoC within the workspace. This can be tested e.g. by building the Zephyr Hello world samples application

cd zephyr/samples/hello_world
west build -b service

After a successful build, Zephyr will create an elf and a bin file of the application in build/zephyr/zephyr.{elf,bin}. The bin file can be converted to a verilog hex file, which in turn can be preloaded to FPGA on-chip memories and run on a target board, or loaded into simulated RAM model when running simulations.

To convert the newly built hello world example into a Verilog hex file, run

python3 $SERV/sw/makehex.py zephyr/samples/hello_world/build/zephyr/zephyr.bin 4096 > hello.hex

4096 is the number of 32-bit words to write and must be at least the size of the application binary. hello.hex is the resulting hex file. Running a simulation can now be done as described in Running pre-built test software, e.g.

fusesoc run --target=verilator_tb servant --uart_baudrate=57600 --firmware=/path/to/hello.hex

Or to create an FPGA image with the application preloaded to on-chip RAM, e.g. for a Nexys A7 board, run

fusesoc run --target=nexys_a7 servant --memfile=/path/to/hello.hex

Good to know

Don't feed serv any illegal instructions after midnight. Many logic expressions are hand-optimized using the old-fashioned method with Karnaugh maps on paper, and shamelessly take advantage of the fact that some opcodes aren't supposed to appear. As serv was written with 4-input LUT FPGAs as target, and opcodes are 5 bits, this can save quite a bit of resources in the decoder.

The bus interface is kind of Wishbone, but with most signals removed. There's an important difference though. Don't send acks on the instruction or data buses unless serv explicitly asks for something by raising its cyc signal. Otherwise serv becomes very confused.

Don't go changing the clock frequency on a whim when running Zephyr. Or well, it's ok I guess, but since the UART is bitbanged, this will change the baud rate as well. As of writing, the UART is running at 115200 baud rate when the CPU is 32 MHz. There are two NOPs in the driver to slow it down a bit, so if those are removed I think it could achieve baud rate 115200 on a 24MHz clock.. in case someone wants to try

serv's Issues

Example code for "8 RISC-V cores and a USB core"?

Hi Olof, a few days ago you announced an interesting result on Twitter:

Can you probably share the code with us? I have a TinyFPGA-BX and would love to try it out. While working on a similar project, I had some problems (e.g. this issue) using tinyfpga_bx_usbserial. Your demo would serve as a great example for me and other beginners.

Lint error "Unnamed generate block"

Running the following command produces lint errors from Verilator:

$ fusesoc run --target=lint serv

INFO: Preparing ::serv:1.2.1
INFO: Setting up project
INFO: Building simulation model
INFO: verilator -f serv_1.2.1.vc -Wall

ERROR: %Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_rf_ram_if.v:65:29: Unnamed generate block 'genblk1' (IEEE 1800-2017 27.6)
                                                              : ... Suggest assign a label with 'begin : gen_<label_name>'
   65 |    generate if (width == 2) begin
      |                             ^~~~~
                     ... For warning description see https://verilator.org/warn/GENUNNAMED?v=5.018
                     ... Use "/* verilator lint_off GENUNNAMED */" and lint_on around source to disable this message.
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_rf_ram_if.v:67:13: Unnamed generate block 'genblk1' (IEEE 1800-2017 27.6)
                                                              : ... Suggest assign a label with 'begin : gen_<label_name>'
   67 |    end else begin
      |             ^~~~~
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_rf_ram_if.v:80:21: Unnamed generate block 'genblk2' (IEEE 1800-2017 27.6)
                                                              : ... Suggest assign a label with 'begin : gen_<label_name>'
   80 |      assign o_waddr = wreg;
      |                     ^
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_rf_ram_if.v:82:21: Unnamed generate block 'genblk2' (IEEE 1800-2017 27.6)
                                                              : ... Suggest assign a label with 'begin : gen_<label_name>'
   82 |      assign o_waddr = {wreg, wcnt[4:l2w]};
      |                     ^
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_rf_ram_if.v:109:21: Unnamed generate block 'genblk3' (IEEE 1800-2017 27.6)
                                                               : ... Suggest assign a label with 'begin : gen_<label_name>'
  109 |      assign o_raddr = rreg;
      |                     ^
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_rf_ram_if.v:111:21: Unnamed generate block 'genblk3' (IEEE 1800-2017 27.6)
                                                               : ... Suggest assign a label with 'begin : gen_<label_name>'
  111 |      assign o_raddr = {rreg, rcnt[4:l2w]};
      |                     ^
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_rf_ram_if.v:125:19: Unnamed generate block 'genblk4' (IEEE 1800-2017 27.6)
                                                               : ... Suggest assign a label with 'begin : gen_<label_name>'
  125 |      assign o_ren = rgate;
      |                   ^
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_rf_ram_if.v:127:19: Unnamed generate block 'genblk4' (IEEE 1800-2017 27.6)
                                                               : ... Suggest assign a label with 'begin : gen_<label_name>'
  127 |      assign o_ren = rgate & (rcnt[l2w-1:1] == 0);
      |                   ^
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_rf_ram_if.v:133:6: Unnamed generate block 'genblk5' (IEEE 1800-2017 27.6)
                                                              : ... Suggest assign a label with 'begin : gen_<label_name>'
  133 |      always @(posedge i_clk) begin
      |      ^~~~~~
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_rf_ram_if.v:139:6: Unnamed generate block 'genblk5' (IEEE 1800-2017 27.6)
                                                              : ... Suggest assign a label with 'begin : gen_<label_name>'
  139 |      always @(posedge i_clk) if (rtrig1) rdata1 <= i_rdata[1];
      |      ^~~~~~
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_top.v:185:18: Unnamed generate block 'genblk1' (IEEE 1800-2017 27.6)
                                                         : ... Suggest assign a label with 'begin : gen_<label_name>'
  185 |       if (ALIGN) begin
      |                  ^~~~~
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_top.v:200:16: Unnamed generate block 'genblk1' (IEEE 1800-2017 27.6)
                                                         : ... Suggest assign a label with 'begin : gen_<label_name>'
  200 |       end else begin
      |                ^~~~~
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_top.v:209:23: Unnamed generate block 'genblk2' (IEEE 1800-2017 27.6)
                                                         : ... Suggest assign a label with 'begin : gen_<label_name>'
  209 |       if (COMPRESSED) begin
      |                       ^~~~~
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_top.v:217:16: Unnamed generate block 'genblk2' (IEEE 1800-2017 27.6)
                                                         : ... Suggest assign a label with 'begin : gen_<label_name>'
  217 |       end else begin
      |                ^~~~~
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_top.v:536:22: Unnamed generate block 'genblk3' (IEEE 1800-2017 27.6)
                                                         : ... Suggest assign a label with 'begin : gen_<label_name>'
  536 |       if (|WITH_CSR) begin
      |                      ^~~~~
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_top.v:570:16: Unnamed generate block 'genblk3' (IEEE 1800-2017 27.6)
                                                         : ... Suggest assign a label with 'begin : gen_<label_name>'
  570 |       end else begin
      |                ^~~~~
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_top.v:648:12: Unnamed generate block 'genblk4' (IEEE 1800-2017 27.6)
                                                         : ... Suggest assign a label with 'begin : gen_<label_name>'
  648 |   if (MDU) begin
      |            ^~~~~
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_top.v:651:12: Unnamed generate block 'genblk4' (IEEE 1800-2017 27.6)
                                                         : ... Suggest assign a label with 'begin : gen_<label_name>'
  651 |   end else begin
      |            ^~~~~
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_alu.v:63:39: Unnamed generate block 'genblk1' (IEEE 1800-2017 27.6)
                                                        : ... Suggest assign a label with 'begin : gen_<label_name>'
   63 |       if (W>1) assign result_slt[B:1] = '0;
      |                                       ^
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_ctrl.v:57:16: Unnamed generate block 'genblk1' (IEEE 1800-2017 27.6)
                                                         : ... Suggest assign a label with 'begin : gen_<label_name>'
   57 |  assign new_pc = i_trap ? (i_csr_pc & !i_cnt0) : i_jump ? pc_plus_offset_aligned : pc_plus_4;
      |                ^
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_ctrl.v:59:16: Unnamed generate block 'genblk1' (IEEE 1800-2017 27.6)
                                                         : ... Suggest assign a label with 'begin : gen_<label_name>'
   59 |  assign new_pc = i_jump ? pc_plus_offset_aligned : pc_plus_4;
      |                ^
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_decode.v:236:25: Unnamed generate block 'genblk1' (IEEE 1800-2017 27.6)
                                                            : ... Suggest assign a label with 'begin : gen_<label_name>'
  236 |       if (PRE_REGISTER) begin
      |                         ^~~~~
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_decode.v:299:16: Unnamed generate block 'genblk1' (IEEE 1800-2017 27.6)
                                                            : ... Suggest assign a label with 'begin : gen_<label_name>'
  299 |       end else begin
      |                ^~~~~
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_immdec.v:36:35: Unnamed generate block 'genblk1' (IEEE 1800-2017 27.6)
                                                           : ... Suggest assign a label with 'begin : gen_<label_name>'
   36 |       if (SHARED_RFADDR_IMM_REGS) begin
      |                                   ^~~~~
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_immdec.v:60:16: Unnamed generate block 'genblk1' (IEEE 1800-2017 27.6)
                                                           : ... Suggest assign a label with 'begin : gen_<label_name>'
   60 |       end else begin
      |                ^~~~~
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_rf_if.v:56:19: Unnamed generate block 'genblk1' (IEEE 1800-2017 27.6)
                                                          : ... Suggest assign a label with 'begin : gen_<label_name>'
   56 |    if (|WITH_CSR) begin
      |                   ^~~~~
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_rf_if.v:122:13: Unnamed generate block 'genblk1' (IEEE 1800-2017 27.6)
                                                           : ... Suggest assign a label with 'begin : gen_<label_name>'
  122 |    end else begin
      |             ^~~~~
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_state.v:207:21: Unnamed generate block 'genblk1' (IEEE 1800-2017 27.6)
                                                           : ... Suggest assign a label with 'begin : gen_<label_name>'
  207 |       if (WITH_CSR) begin
      |                     ^~~~~
%Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_state.v:221:28: Unnamed generate block 'genblk1' (IEEE 1800-2017 27.6)
                                                           : ... Suggest assign a label with 'begin : gen_<label_name>'
  221 |  assign misalign_trap_sync = 1'b0;
      |                            ^
%Error: Exiting due to 29 warning(s)
make: *** [Makefile:16: Vserv_rf_top.mk] Error 1

ERROR: Failed to build ::serv:1.2.1 : '['make', 'Vserv_rf_top.mk']' exited with an error: 2

These are the versions of SERV, Verilator, and FuseSoC:

$ git rev-parse --short HEAD # in $workspace/fusesoc_libraries/serv
c7fc572
$ verilator --version
Verilator 5.018 2023-10-30 rev UNKNOWN.REV
$ fusesoc --version
2.2.1

I followed the steps outlined in the README:

$ python -m venv venv && . venv/bin/activate
$ pip install fusesoc
$ fusesoc library add fusesoc_cores https://github.com/fusesoc/fusesoc-cores
$ fusesoc library add serv https://github.com/olofk/serv

I think these might be relevant to the error:

• https://stackoverflow.com/questions/8564237/what-does-it-mean-vcs-has-encountered-unamed-generate-blocks
• YosysHQ/yosys#656

I'm opening this issue because I think the author(s) intend the RTL to pass the linter, so I wanted to know if I'm missing anything obvious. Any help would be appreciated.

privilege tests failing for uncompressed SERV

In PR #79, the serv_aligner module is turned on only if the SERV is compiled with the support of Compressed instruction i.e. compressed=1. In order to pass the privilege tests, the serv_aligner module must be part of SERV core irrespective of the support of compressed instructions.

No tool was supplied on command line or found in 'servant' core description

When running fusesoc run --target=ulx3s servant for the for the ULX3S, I see this error:

ERROR: No tool was supplied on command line or found in 'servant' core description

gojimmypi@DESKTOP(WSL): /mnt/c/workspace ()

0 $  mkdir fusesoc-ulx3s
gojimmypi@DESKTOP(WSL): /mnt/c/workspace ()

0 $  cd fusesoc-ulx3s
gojimmypi@DESKTOP(WSL): /mnt/c/workspace/fusesoc-ulx3s ()

0 $  fusesoc library add serv https://github.com/olofk/serv
WARNING: The CAPI1 core file description format is deprecated and will be removed in the next major version of FuseSoC. Please port your core files to the CAPI2 format.
fusesoc.conf
INFO: Cloning library into fusesoc_libraries/serv
Cloning into 'fusesoc_libraries/serv'...
remote: Enumerating objects: 2277, done.
remote: Counting objects: 100% (518/518), done.
remote: Compressing objects: 100% (281/281), done.
remote: Total 2277 (delta 307), reused 366 (delta 227), pack-reused 1759
Receiving objects: 100% (2277/2277), 5.11 MiB | 4.01 MiB/s, done.
Resolving deltas: 100% (1429/1429), done.
gojimmypi@DESKTOP(WSL): /mnt/c/workspace/fusesoc-ulx3s ()

0 $  fusesoc library add fusesoc_cores https://github.com/fusesoc/fusesoc-cores
WARNING: The CAPI1 core file description format is deprecated and will be removed in the next major version of FuseSoC. Please port your core files to the CAPI2 format.
fusesoc.conf
INFO: Cloning library into fusesoc_libraries/fusesoc_cores
Cloning into 'fusesoc_libraries/fusesoc_cores'...
remote: Enumerating objects: 670, done.
remote: Counting objects: 100% (221/221), done.
remote: Compressing objects: 100% (154/154), done.
remote: Total 670 (delta 97), reused 175 (delta 55), pack-reused 449
Receiving objects: 100% (670/670), 144.79 KiB | 1.57 MiB/s, done.
Resolving deltas: 100% (241/241), done.
gojimmypi@DESKTOP(WSL): /mnt/c/workspace/fusesoc-ulx3s ()

0 $  fusesoc run --target=ulx3s servant
WARNING: The CAPI1 core file description format is deprecated and will be removed in the next major version of FuseSoC. Please port your core files to the CAPI2 format.
ERROR: No tool was supplied on command line or found in 'servant' core description

yet it works fine for the tinyfpga-bx:

gojimmypi@DESKTOP(WSL): /mnt/c/workspace/fusesoc-ulx3s ()

0 $  fusesoc run --target=tinyfpga_bx servant
WARNING: The CAPI1 core file description format is deprecated and will be removed in the next major version of FuseSoC. Please port your core files to the CAPI2 format.
INFO: Preparing fusesoc:utils:generators:0.1.7
INFO: Preparing ::serv:1.1.0
INFO: Preparing ::servant:1.1.0
INFO: Generating ::servant-tinyfpga_bx_pll:1.1.0

F_PLLIN:    16.000 MHz (given)
F_PLLOUT:   32.000 MHz (requested)
F_PLLOUT:   32.000 MHz (achieved)

...[snip]...

Info: [ 27230,  27986) |********************+
Info: [ 27986,  28742) |**************+
Info: [ 28742,  29498) |****************************************+
icepack servant_1.1.0_next.asc servant_1.1.0.bin
INFO: Running

The problem seems to be the definitions of boards missing a PCF file type, such as the ulx3s:

  ulx3s:
    files:
      - ulx3s/ulx3s_v20.lpf : {file_type : LPF, copyto : ulx3s_v20.lpf}
      - ulx3s/blinky_ulx3s.v : {file_type : verilogSource}

As the zcu102 also fails:

0 $  fusesoc run --target=zcu102 servant
WARNING: The CAPI1 core file description format is deprecated and will be removed in the next major version of FuseSoC. Please port your core files to the CAPI2 format.
ERROR: No tool was supplied on command line or found in 'servant' core description

... and others also fail:

gojimmypi@DESKTOP(WSL): /mnt/c/workspace/fusesoc-ulx3s ()

0 $  fusesoc run --target=eclypse_z7 servant
WARNING: The CAPI1 core file description format is deprecated and will be removed in the next major version of FuseSoC. Please port your core files to the CAPI2 format.
ERROR: No tool was supplied on command line or found in 'servant' core description
gojimmypi@DESKTOP(WSL): /mnt/c/workspace/fusesoc-ulx3s ()

0 $  fusesoc run --target=fomu-pvt servant
WARNING: The CAPI1 core file description format is deprecated and will be removed in the next major version of FuseSoC. Please port your core files to the CAPI2 format.
ERROR: No tool was supplied on command line or found in 'servant' core description
gojimmypi@DESKTOP(WSL): /mnt/c/workspace/fusesoc-ulx3s ()

But note the icebreaker, with a PCF

  icebreaker:
    files: [icebreaker/pinout.pcf : {file_type : PCF}]

is successful:

0 $  fusesoc run --target=icebreaker servant
WARNING: The CAPI1 core file description format is deprecated and will be removed in the next major version of FuseSoC. Please port your core files to the CAPI2 format.
INFO: Preparing fusesoc:utils:generators:0.1.7
INFO: Preparing ::serv:1.1.0
INFO: Preparing ::servant:1.1.0
INFO: Generating ::servant-icebreaker_pll:1.1.0

F_PLLIN:    12.000 MHz (given)
F_PLLOUT:   16.000 MHz (requested)
F_PLLOUT:   15.938 MHz (achieved)

I also tried the blinky directories that contained the ulx3s files, but all with the same error:

git clone https://github.com/fusesoc/blinky.git fusesoc-blinky
cd fusesoc-blinky/cd ulx3s
fusesoc run --target=ulx3s servant

fusesoc library add serv https://github.com/olofk/serv
fusesoc library add fusesoc_cores https://github.com/fusesoc/fusesoc-cores
fusesoc run --target=ulx3s servant

cd ..
fusesoc library add fusesoc_cores https://github.com/fusesoc/fusesoc-cores
fusesoc library add serv https://github.com/olofk/serv
fusesoc run --target=ulx3s servant

fusesoc run --target=tinyfpga_bx servant
fusesoc run --target=ulx3s servant
fusesoc run --target=ulx3s

Of course, I'm left wondering about the WARNING: The CAPI1 core file description format is deprecated and will be removed in the next major version of FuseSoC. Please port your core files to the CAPI2 format..

• edit: here's my current fusesoc version, apparently already up to date at version 1.12.0 per the installation docs:

0 $   fusesoc --version
1.12.0
gojimmypi@DESKTOP(WSL): /mnt/c/workspace/fusesoc-ulx3s ()

0 $  pip3 install --upgrade --user fusesoc
Requirement already up-to-date: fusesoc in /home/gojimmypi/.local/lib/python3.8/site-packages (1.12.0)
Requirement already satisfied, skipping upgrade: edalize>=0.2.3 in /home/gojimmypi/.local/lib/python3.8/site-packages (from fusesoc) (0.2.5)
Requirement already satisfied, skipping upgrade: ipyxact>=0.2.3 in /home/gojimmypi/.local/lib/python3.8/site-packages (from fusesoc) (0.2.4)
Requirement already satisfied, skipping upgrade: pyyaml in /usr/lib/python3/dist-packages (from fusesoc) (5.3.1)
Requirement already satisfied, skipping upgrade: pyparsing in /home/gojimmypi/.local/lib/python3.8/site-packages (from fusesoc) (2.4.7)
Requirement already satisfied, skipping upgrade: simplesat>=0.8.0 in /home/gojimmypi/.local/lib/python3.8/site-packages (from fusesoc) (0.8.2)
Requirement already satisfied, skipping upgrade: Jinja2>=2.11.3 in /home/gojimmypi/.local/lib/python3.8/site-packages (from edalize>=0.2.3->fusesoc) (3.0.1)
Requirement already satisfied, skipping upgrade: attrs>=17.4.0 in /usr/lib/python3/dist-packages (from simplesat>=0.8.0->fusesoc) (19.3.0)
Requirement already satisfied, skipping upgrade: six>=1.10.0 in /usr/lib/python3/dist-packages (from simplesat>=0.8.0->fusesoc) (1.14.0)
Requirement already satisfied, skipping upgrade: okonomiyaki>=0.16.6 in /home/gojimmypi/.local/lib/python3.8/site-packages (from simplesat>=0.8.0->fusesoc) (1.3.0)
Requirement already satisfied, skipping upgrade: MarkupSafe>=2.0 in /home/gojimmypi/.local/lib/python3.8/site-packages (from Jinja2>=2.11.3->edalize>=0.2.3->fusesoc) (2.0.1)
Requirement already satisfied, skipping upgrade: zipfile2>=0.0.12 in /home/gojimmypi/.local/lib/python3.8/site-packages (from okonomiyaki>=0.16.6->simplesat>=0.8.0->fusesoc) (0.0.12)
Requirement already satisfied, skipping upgrade: jsonschema>=2.5.1 in /usr/lib/python3/dist-packages (from okonomiyaki>=0.16.6->simplesat>=0.8.0->fusesoc) (3.2.0)

Add a step for yosysSynthesisReport() to Jenkinsfile

Extend the use case of yosysSynthesisReport() to serv project from Librecores pipeline library : https://github.com/librecores/librecores-pipeline-lib

Example for Reference : https://github.com/openrisc/mor1kx/blob/master/Jenkinsfile ,
https://ci.librecores.org/job/Projects/job/OpenRISC/job/mor1kx/job/master/plot/Resource%20Usage/

Linux compatibility

Does this core be able to run linux on it?

Declare variables/nets before referenced

Modelsim tends to get quite angry when it sees a variable that is not declared.

serv_decode.v: "op_or_opimm"
serv_immdec.v: "signbit"
serv_top.v: "dbus_rdt"
Can we move them before they are referenced?

This has happened after 6e802cb

Add all presentations and YouTube videos to the end of the README file.

Hi,
I think it would be a good idea to add and update all presentations/videos about the SERV to the end of the README file so people can have a link to all of them in case they need.

Unable to run Compliance Tests

ls: cannot access '/home/ashvin/thesis/workspace/riscv-arch-test/riscv-target/serv/device/rv32i_m': No such file or directory

============================ VARIABLE INFO ==================================
ROOTDIR: /home/ashvin/thesis/workspace/riscv-arch-test [origin: file]
WORK: /home/ashvin/thesis/workspace/riscv-arch-test/work [origin: file]
TARGETDIR: /home/ashvin/thesis/workspace/riscv-arch-test/riscv-target [origin: command line]
RISCV_TARGET: serv [origin: command line]
XLEN: 32 [origin: file]
RISCV_DEVICE: I [origin: command line]
=============================================================================

make -j1 \
	RISCV_TARGET=serv \
	RISCV_DEVICE=I \
	run -C /home/ashvin/thesis/workspace/riscv-arch-test/riscv-test-suite/rv32i_m/I
make[1]: Entering directory '/home/ashvin/thesis/workspace/riscv-arch-test/riscv-test-suite/rv32i_m/I'
../../Makefile.include:25: *** Cannot find '/home/ashvin/thesis/workspace/riscv-arch-test/riscv-target/serv/device/rv32i_m/I/Makefile.include`. Check that RISCV_TARGET and RISCV_DEVICE are set correctly..  Stop.
make[1]: Leaving directory '/home/ashvin/thesis/workspace/riscv-arch-test/riscv-test-suite/rv32i_m/I'
make: *** [Makefile:84: simulate] Error 2

As far as I understand I am supposed to point the test to the files built by fusesoc, but there is no such directory once the build is finished. Can someone point me out to where I am going wrong?

RISCV Compliance fails

Working through the README in the Serv top level I'm failing to get RISCV compliance to run. There appear to be discrepencies between the number of arguments passed to macro's defined in serv/riscv-target/serv/compliance_io.h and the way they are used in the rv32i compliance tests.

Brief snippet:

(fusesoc) ianb@cruncher:~/src/olofk/riscv-compliance$ cd $SERV/riscv-compliance && make TARGETDIR=$SERV/serv/riscv-target RISCV_TARGET=serv RISCV_DECICE=rv32i RISCV_ISA=rv32i TARGET_SIM=$SERV/workspace/build/servant_1.0.1/verilator_tb-verilator/Vservant_sim
make
RISCV_TARGET=serv
RISCV_DEVICE=rv32i
RISCV_PREFIX=riscv64-unknown-elf-
run -C /home/ianb/src/olofk/riscv-compliance/riscv-test-suite/rv32i
make[1]: Entering directory '/home/ianb/src/olofk/riscv-compliance/riscv-test-suite/rv32i'
Compile /home/ianb/src/olofk/riscv-compliance/work/rv32i/I-ENDIANESS-01.elf
src/I-ENDIANESS-01.S:43:48: error: macro "RVTEST_IO_ASSERT_GPR_EQ" passed 3 arguments, but takes just 2
43 | RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
| ^
In file included from src/I-ENDIANESS-01.S:33:
/home/ianb/src/olofk/serv/riscv-target/serv/compliance_io.h:32: note: macro "RVTEST_IO_ASSERT_GPR_EQ" defined here
32 | #define RVTEST_IO_ASSERT_GPR_EQ(_R, _I)
|
src/I-ENDIANESS-01.S:44:46: error: macro "RVTEST_IO_WRITE_STR" passed 2 arguments, but takes just 1
44 | RVTEST_IO_WRITE_STR(x31, "# Test Begin\n")
| ^
In file included from src/I-ENDIANESS-01.S:33:
/home/ianb/src/olofk/serv/riscv-target/serv/compliance_io.h:30: note: macro "RVTEST_IO_WRITE_STR" defined here
30 | #define RVTEST_IO_WRITE_STR(_STR)
|

There seems to be a similar discrepancy in the rocket target supplied with the RISCV Compliance tests:

riscv-target/rocket/compliance_io.h:#define RVTEST_IO_ASSERT_GPR_EQ(_R, _I)

But all other targets declare 3 arguments:

riscv-target/sail-riscv-c/compliance_io.h:#define RVTEST_IO_ASSERT_GPR_EQ(_SP, _R, _I)
riscv-target/grift/compliance_io.h:#define RVTEST_IO_ASSERT_GPR_EQ(_SP, _R, _I)
riscv-target/sail-riscv-ocaml/compliance_io.h:#define RVTEST_IO_ASSERT_GPR_EQ(_SP, _R, _I)
riscv-target/sifive-formal/compliance_io.h:#define RVTEST_IO_ASSERT_GPR_EQ(_G, _R, _I)
riscv-target/spike/compliance_io.h:#define RVTEST_IO_ASSERT_GPR_EQ(_SP, _R, _I)
riscv-target/ri5cy/compliance_io.h:#define RVTEST_IO_ASSERT_GPR_EQ(_SP, _R, _I)
riscv-target/ri5cy/compliance_io.h:#define RVTEST_IO_ASSERT_GPR_EQ(_SP, _R, _I)
riscv-target/Codasip-simulator/compliance_io.h:#define RVTEST_IO_ASSERT_GPR_EQ(_SP, _R, _I)
riscv-target/ibex/compliance_io.h:#define RVTEST_IO_ASSERT_GPR_EQ(_SP, _R, _I)
riscv-target/riscvOVPsim/compliance_io.h:#define RVTEST_IO_ASSERT_GPR_EQ(_SP, _R, _I)
riscv-target/riscvOVPsim/compliance_io.h:#define RVTEST_IO_ASSERT_GPR_EQ(_SP, _R, _I)

Just a question building Zephyr demos.

Hi Olof,

Thanks for serv!
Yesterday I managed to get the serv core running with the hello world example, running 72Mhz using on a Tang Nano 9K and getting the Hello World @ 259200 baud.

Next step would be change the Hello World application to something useful.

Never used west before, any quick commands that will generate a servant risc-v binary from source?

H

Unitialized signals on Modelsim

There is a signal initialization problem on Modelsim. Icarus Verilog is working without a problem.
The problem is not new. I have been using serv since July and it also existed back then. Resetting the MTIE register solves the problem.

serv/rtl/serv_csr.v

Lines 136 to 137 in 99f82af

	if (RESET_STRATEGY != "NONE")
	o_new_irq <= 1'b0;

Solution:

	if (RESET_STRATEGY != "NONE")
			o_new_irq <= 1'b0;
+			mie_mtie <= 1'b0;

ModelSim - Intel FPGA Starter Edition 20.1.0.711
The code used during testing:

.globl __start
__start:

.text
li t4,0x80000000 
li t3,12000
li t6,12000
sw t3,0(t4)
la t0,interrupt_handler
csrrw zero, mtvec, t0
li	a4,128
csrrs	a4,mie,a4
csrsi	mstatus,8
hh:
    li t4,0x40000000 
    li t3,69696969
    sw t3,0(t4)
j hh

interrupt_handler:
    li t4,0x80000000
    li t0,12000  
    add t6,t6,t0
    sw t6,0(t4)
    li t4,0x40000000 
    li t3,1111111
    sw t3,0(t4)


    mret

SERV fails with other codes too. Like hello.hex: https://github.com/olofk/subservient/blob/55cb5a1d9c1586e59d848ee20d5429175ce47c8c/sw/hello.hex#L1-L12 )

Error running pre-built test software: bad path, missing files

When trying the Running pre-built test software , I encountered this error:

ERROR: Failed to build ::servant:1.0.2-r1 : '['make', '-j', '16']' exited with an error: 2 as shown below.

0 $  mkdir vs-fusesoc
gojimmypi@DESKTOP(WSL): /mnt/c/workspace ()

0 $  cd vs-fusesoc
gojimmypi@DESKTOP(WSL): /mnt/c/workspace/vs-fusesoc ()

0 $  fusesoc library add fusesoc_cores https://github.com/fusesoc/fusesoc-cores
WARNING: The CAPI1 core file description format is deprecated and will be removed in the next major version of FuseSoC. Please port your core files to the CAPI2 format.
fusesoc.conf
INFO: Cloning library into fusesoc_libraries/fusesoc_cores
Cloning into 'fusesoc_libraries/fusesoc_cores'...
remote: Enumerating objects: 670, done.
remote: Counting objects: 100% (221/221), done.
remote: Compressing objects: 100% (154/154), done.
remote: Total 670 (delta 97), reused 175 (delta 55), pack-reused 449
Receiving objects: 100% (670/670), 144.79 KiB | 1.10 MiB/s, done.
Resolving deltas: 100% (241/241), done.
gojimmypi@DESKTOP(WSL): /mnt/c/workspace/vs-fusesoc ()

0 $  ls
fusesoc.conf  fusesoc_libraries
gojimmypi@DESKTOP(WSL): /mnt/c/workspace/vs-fusesoc ()

0 $  fusesoc run --target=lint serv
WARNING: The CAPI1 core file description format is deprecated and will be removed in the next major version of FuseSoC. Please port your core files to the CAPI2 format.
INFO: Preparing ::serv:1.0.2
INFO: Downloading olofk/serv from github
INFO: Setting up project

INFO: Building simulation model
verilator -f serv_1.0.2.vc
INFO: Running
gojimmypi@DESKTOP(WSL): /mnt/c/workspace/vs-fusesoc ()

0 $  fusesoc run --target=verilator_tb servant --uart_baudrate=57600 --firmware=$SERV/sw/zephyr_hello.hex
WARNING: The CAPI1 core file description format is deprecated and will be removed in the next major version of FuseSoC. Please port your core files to the CAPI2 format.
INFO: Preparing ::serv:1.0.2
INFO: Preparing ::vlog_tb_utils:1.1-r1
INFO: Preparing ::servant:1.0.2-r1
INFO: Downloading olofk/serv from github
INFO: Setting up project

INFO: Building simulation model
verilator -f servant_1.0.2-r1.vc --trace
%Warning-STMTDLY: ../src/vlog_tb_utils_1.1-r1/vlog_tb_utils.v:27: Unsupported: Ignoring delay on this delayed statement.
 #timeout $display("Timeout: Forcing end of simulation");
 ^
                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.
%Error: ../src/vlog_tb_utils_1.1-r1/vlog_tb_utils.v:37: Unsupported or unknown PLI call: $dumpfile
    $dumpfile({testcase,".vcd"});
    ^~~~~~~~~
%Error: ../src/vlog_tb_utils_1.1-r1/vlog_tb_utils.v:39: Unsupported or unknown PLI call: $dumpfile
    $dumpfile("testlog.vcd");
    ^~~~~~~~~
%Error: ../src/vlog_tb_utils_1.1-r1/vlog_tb_utils.v:40: Unsupported or unknown PLI call: $dumpvars
  $dumpvars;
  ^~~~~~~~~
%Warning-STMTDLY: ../src/vlog_tb_utils_1.1-r1/vlog_tb_utils.v:48: Unsupported: Ignoring delay on this delayed statement.
 forever #heartbeat $display("Heartbeat : Time=%0t", $time);
         ^
%Error: Exiting due to 3 error(s), 2 warning(s)
        ... See the manual and https://verilator.org for more assistance.
make: *** [Makefile:16: Vservant_sim.mk] Error 1
ERROR: Failed to build ::servant:1.0.2-r1 : '['make', '-j', '16']' exited with an error: 2

I also tried manually setting a $SERV environment variable, but same result:

0 $  export WORKSPACE=/mnt/c/workspace/vs-fusesoc
gojimmypi@DESKTOP(WSL): /mnt/c/workspace/vs-fusesoc ()

0 $  export SERV=$WORKSPACE/fusesoc_libraries/serv
gojimmypi@DESKTOP(WSL): /mnt/c/workspace/vs-fusesoc ()

0 $  echo $SERV
/mnt/c/workspace/vs-fusesoc/fusesoc_libraries/serv
gojimmypi@DESKTOP(WSL): /mnt/c/workspace/vs-fusesoc ()

0 $  fusesoc run --target=verilator_tb servant --uart_baudrate=57600 --firmware=$SERV/sw/zephyr_hello.hex
WARNING: The CAPI1 core file description format is deprecated and will be removed in the next major version of FuseSoC. Please port your core files to the CAPI2 format.
INFO: Preparing ::serv:1.0.2
INFO: Preparing ::vlog_tb_utils:1.1-r1
INFO: Preparing ::servant:1.0.2-r1
INFO: Setting up project

INFO: Building simulation model
verilator -f servant_1.0.2-r1.vc --trace
%Warning-STMTDLY: ../src/vlog_tb_utils_1.1-r1/vlog_tb_utils.v:27: Unsupported: Ignoring delay on this delayed statement.
 #timeout $display("Timeout: Forcing end of simulation");
 ^
                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.
%Error: ../src/vlog_tb_utils_1.1-r1/vlog_tb_utils.v:37: Unsupported or unknown PLI call: $dumpfile
    $dumpfile({testcase,".vcd"});
    ^~~~~~~~~
%Error: ../src/vlog_tb_utils_1.1-r1/vlog_tb_utils.v:39: Unsupported or unknown PLI call: $dumpfile
    $dumpfile("testlog.vcd");
    ^~~~~~~~~
%Error: ../src/vlog_tb_utils_1.1-r1/vlog_tb_utils.v:40: Unsupported or unknown PLI call: $dumpvars
  $dumpvars;
  ^~~~~~~~~
%Warning-STMTDLY: ../src/vlog_tb_utils_1.1-r1/vlog_tb_utils.v:48: Unsupported: Ignoring delay on this delayed statement.
 forever #heartbeat $display("Heartbeat : Time=%0t", $time);
         ^
%Error: Exiting due to 3 error(s), 2 warning(s)
        ... See the manual and https://verilator.org for more assistance.
make: *** [Makefile:16: Vservant_sim.mk] Error 1
ERROR: Failed to build ::servant:1.0.2-r1 : '['make', '-j', '16']' exited with an error: 2
gojimmypi@DESKTOP(WSL): /mnt/c/workspace/vs-fusesoc ()

It appears the problem is in part that there is not actually a $WORKSPACE/fusesoc_libraries/serv directory as described in the Prerequisites:

The SERV repo will now be available in $WORKSPACE/fusesoc_libraries/serv. To save some typing, we will refer to that directory as $SERV.

0 $  ls $SERV
ls: cannot access '/mnt/c/workspace/vs-fusesoc/fusesoc_libraries/serv': No such file or directory
gojimmypi@DESKTOP(WSL): /mnt/c/workspace/vs-fusesoc ()

0 $  ls
build  fusesoc.conf  fusesoc_libraries
gojimmypi@DESKTOP(WSL): /mnt/c/workspace/vs-fusesoc ()

0 $  ls fusesoc_libraries
fusesoc_cores
gojimmypi@DESKTOP(WSL): /mnt/c/workspace/vs-fusesoc ()

In fact, there was no sw directory at all, and no files ended in .hex in the entire directory structure.

Stuck in loading RAM

Is loading hex file very long ? Because regardless of README.md command I launch its stuck in step "loading RAM".

• zephyr hello :

 fusesoc run --target=verilator_tb servant --uart_baudrate=57600 --firmware=$SERV/sw/zephyr_hello.hex
INFO: Preparing ::serv:0
INFO: Preparing ::servant:0
[...]
ranlib Vservant__ALL.a
g++    servant_tb.o verilated.o verilated_dpi.o verilated_vcd_c.o Vservant__ALL.a    -o Vservant -lm -lstdc++  2>&1 | c++filt
make[1]: Leaving directory '/home/fabien/myfpga/serv_virgin/workspace/build/servant_0/verilator_tb-verilator'
Loading RAM from /home/fabien/myfpga/serv_virgin/sw/zephyr_hello.hex

• Zephyr hello multi thread :

 fusesoc run --target=verilator_tb servant --uart_baudrate=57600 --firmware=$SERV/sw/zephyr_hello_mt.hex --memsize=16384
INFO: Preparing ::serv:0
INFO: Preparing ::servant:0
[...]
g++    servant_tb.o verilated.o verilated_dpi.o verilated_vcd_c.o Vservant__ALL.a    -o Vservant -lm -lstdc++  2>&1 | c++filt
make[1]: Leaving directory '/home/fabien/myfpga/serv_virgin/workspace/build/servant_0/verilator_tb-verilator'
Loading RAM from /home/fabien/myfpga/serv_virgin/sw/zephyr_hello_mt.hex

Even if I'm waiting for several minutes it stay stuck.

Missing Zero Hardwire of register "x0"

Hi Olof,

First of all, congratulations on the work with this remarkable RISC-V implementation. I am working on an ASIC friendly version for a 65nm tapeout. I ran into an issue when using a simulation environment without default initialization on memories and registers. In the very end, the issue was due to the lack of a hardwired value zero of register in address 0. A simple fix for this issue was to change the line in:

serv/rtl/serv_rf_ram.v

Line 17 in 4a5c5bd

o_rdata <= memory[i_raddr];

to something like:

       // register x0 is hardwired to zero (assumes width will be power of two)
        o_rdata <= (|i_raddr[$clog2(depth)-1:$clog2(32/width)]) ? memory[i_raddr] : {(width){1'b0}};

One last thing. If I publish a paper, how would you like to be referenced?

Thanks for your work!
Hugo

Does fusesoc work on Windows? (regular DOS, not WSL)

As noted in #83 I had some problems installing fusesoc in WSL due to a default python version issue.

I next tried to use Windows. I don't have Verilator installed, as apparently only Linux versions on supported per the install guide. So, perhaps the first error (below) for fusesoc run --target=lint serv is expected, although the error presented does not appear to be related to Verilator.

Does Verilator generate the verilator_tb file? I also saw another error for fusesoc run (see below).

Granted, the instructions state: 'If Verilator is installed, we can use that as a linter to check the SERV source code` - but is that for only that particular linting step, or all steps?

C:\workspace\myfusesoc> pip install fusesoc
Requirement already satisfied: fusesoc in c:\users\gojimmypi\appdata\local\programs\python\python38-32\lib\site-packages (1.12.0)
Requirement already satisfied: simplesat>=0.8.0 in c:\users\gojimmypi\appdata\local\programs\python\python38-32\lib\site-packages (from fusesoc) (0.8.2)
Requirement already satisfied: pyparsing in c:\users\gojimmypi\appdata\local\programs\python\python38-32\lib\site-packages (from fusesoc) (3.0.9)
Requirement already satisfied: edalize>=0.2.3 in c:\users\gojimmypi\appdata\local\programs\python\python38-32\lib\site-packages (from fusesoc) (0.4.0)
Requirement already satisfied: ipyxact>=0.2.3 in c:\users\gojimmypi\appdata\local\programs\python\python38-32\lib\site-packages (from fusesoc) (0.3.2)
Requirement already satisfied: pyyaml in c:\users\gojimmypi\appdata\local\programs\python\python38-32\lib\site-packages (from fusesoc) (6.0)
Requirement already satisfied: okonomiyaki>=0.16.6 in c:\users\gojimmypi\appdata\local\programs\python\python38-32\lib\site-packages (from simplesat>=0.8.0->fusesoc) (1.3.2)
Requirement already satisfied: attrs>=17.4.0 in c:\users\gojimmypi\appdata\local\programs\python\python38-32\lib\site-packages (from simplesat>=0.8.0->fusesoc) (21.4.0)
Requirement already satisfied: six>=1.10.0 in c:\users\gojimmypi\appdata\local\programs\python\python38-32\lib\site-packages (from simplesat>=0.8.0->fusesoc) (1.16.0)
Requirement already satisfied: Jinja2>=3 in c:\users\gojimmypi\appdata\local\programs\python\python38-32\lib\site-packages (from edalize>=0.2.3->fusesoc) (3.1.2)
Requirement already satisfied: zipfile2>=0.0.12 in c:\users\gojimmypi\appdata\local\programs\python\python38-32\lib\site-packages (from okonomiyaki>=0.16.6->simplesat>=0.8.0->fusesoc) (0.0.12)
Requirement already satisfied: jsonschema>=2.5.1 in c:\users\gojimmypi\appdata\local\programs\python\python38-32\lib\site-packages (from okonomiyaki>=0.16.6->simplesat>=0.8.0->fusesoc) (4.7.2)
Requirement already satisfied: distro; python_version >= "3.8" in c:\users\gojimmypi\appdata\local\programs\python\python38-32\lib\site-packages (from okonomiyaki>=0.16.6->simplesat>=0.8.0->fusesoc) (1.7.0)
Requirement already satisfied: MarkupSafe>=2.0 in c:\users\gojimmypi\appdata\local\programs\python\python38-32\lib\site-packages (from Jinja2>=3->edalize>=0.2.3->fusesoc) (2.1.1)
Requirement already satisfied: pyrsistent!=0.17.0,!=0.17.1,!=0.17.2,>=0.14.0 in c:\users\gojimmypi\appdata\local\programs\python\python38-32\lib\site-packages (from jsonschema>=2.5.1->okonomiyaki>=0.16.6->simplesat>=0.8.0->fusesoc) (0.18.1)
Requirement already satisfied: importlib-resources>=1.4.0; python_version < "3.9" in c:\users\gojimmypi\appdata\local\programs\python\python38-32\lib\site-packages (from jsonschema>=2.5.1->okonomiyaki>=0.16.6->simplesat>=0.8.0->fusesoc) (5.9.0)
Requirement already satisfied: zipp>=3.1.0; python_version < "3.10" in c:\users\gojimmypi\appdata\local\programs\python\python38-32\lib\site-packages (from importlib-resources>=1.4.0; python_version < "3.9"->jsonschema>=2.5.1->okonomiyaki>=0.16.6->simplesat>=0.8.0->fusesoc) (3.8.1)
WARNING: You are using pip version 19.2.3, however version 22.1.2 is available.
You should consider upgrading via the 'python -m pip install --upgrade pip' command.

C:\workspace\myfusesoc> fusesoc library add fusesoc_cores https://github.com/fusesoc/fusesoc-cores
←[1;37mINFO: Cloning library into fusesoc_libraries\fusesoc_cores←[0m
Cloning into 'fusesoc_libraries\fusesoc_cores'...
remote: Enumerating objects: 678, done.
remote: Counting objects: 100% (101/101), done.
remote: Compressing objects: 100% (26/26), done.
Receiving objects:  88% (597/678)used 78 (delta 75), pack-reused 577
Receiving objects: 100% (678/678), 141.02 KiB | 2.76 MiB/s, done.
Resolving deltas: 100% (265/265), done.

C:\workspace\myfusesoc>fusesoc library add serv https://github.com/olofk/serv
←[1;37mINFO: Cloning library into fusesoc_libraries\serv←[0m
Cloning into 'fusesoc_libraries\serv'...
remote: Enumerating objects: 2471, done.
remote: Counting objects: 100% (583/583), done.
remote: Compressing objects: 100% (187/187), done.
remote: Total 2471 (delta 458), reused 417 (delta 393), pack-reused 1888
Receiving objects: 100% (2471/2471), 5.27 MiB | 9.01 MiB/s, done.
Resolving deltas: 100% (1585/1585), done.

C:\workspace\myfusesoc>fusesoc run --target=lint serv
←[1;37mINFO: Preparing ::serv:1.1.0←[0m
←[1;37mINFO: Setting up project←[0m

←[1;37mINFO: Building simulation model←[0m
verilator -f serv_1.1.0.vc -Wall
process_begin: CreateProcess(NULL, verilator -f serv_1.1.0.vc -Wall, ...) failed.
make (e=2): The system cannot find the file specified.
make: *** [Makefile:16: Vserv_rf_top.mk] Error 2
←[1;31mERROR: Failed to build ::serv:1.1.0 : '['make', 'Vserv_rf_top.mk']' exited with an error: 2←[0m

C:\workspace\myfusesoc>verilator
'verilator' is not recognized as an internal or external command,
operable program or batch file.

C:\workspace\myfusesoc>fusesoc run --target=verilator_tb servant --uart_baudrate=57600 --firmware=$SERV/sw/zephyr_hello.hex
←[1;37mINFO: Preparing ::serv:1.1.0←[0m
←[1;37mINFO: Preparing ::servant:1.1.0←[0m
←[1;37mINFO: Setting up project←[0m

←[1;37mINFO: Building simulation model←[0m
verilator -f servant_1.1.0.vc --trace
process_begin: CreateProcess(NULL, verilator -f servant_1.1.0.vc --trace, ...) failed.
make (e=2): The system cannot find the file specified.
make: *** [Makefile:16: Vservant_sim.mk] Error 2
←[1;31mERROR: Failed to build ::servant:1.1.0 : '['make']' exited with an error: 2←[0m

WSL install, permission denied for fusesoc.conf, saved to current directory

This appears to be a relative path, or perhaps even path case problem.

Yes, please don't leave the room screaming when reading about case sensitivity. lol ;)

The default directory for WSL is /mnt/c/Windows/System32 when first launching WSL on Windows 10.

When running fusesoc library add from the default directory, an error is encountered:

gojimmypi@DESKTOP(WSL): /mnt/c/Windows/System32 ()

0 $  pip install fusesoc
Requirement already satisfied: fusesoc in /home/gojimmypi/.local/lib/python3.8/site-packages (1.12.0)
Requirement already satisfied: pyparsing in /home/gojimmypi/.local/lib/python3.8/site-packages (from fusesoc) (2.4.7)
Requirement already satisfied: ipyxact>=0.2.3 in /home/gojimmypi/.local/lib/python3.8/site-packages (from fusesoc) (0.2.4)
Requirement already satisfied: simplesat>=0.8.0 in /home/gojimmypi/.local/lib/python3.8/site-packages (from fusesoc) (0.8.2)
Requirement already satisfied: pyyaml in /usr/lib/python3/dist-packages (from fusesoc) (5.3.1)
Requirement already satisfied: edalize>=0.2.3 in /home/gojimmypi/.local/lib/python3.8/site-packages (from fusesoc) (0.2.5)
Requirement already satisfied: attrs>=17.4.0 in /usr/lib/python3/dist-packages (from simplesat>=0.8.0->fusesoc) (19.3.0)Requirement already satisfied: six>=1.10.0 in /usr/lib/python3/dist-packages (from simplesat>=0.8.0->fusesoc) (1.14.0)
Requirement already satisfied: okonomiyaki>=0.16.6 in /home/gojimmypi/.local/lib/python3.8/site-packages (from simplesat>=0.8.0->fusesoc) (1.3.0)
Requirement already satisfied: Jinja2>=2.11.3 in /home/gojimmypi/.local/lib/python3.8/site-packages (from edalize>=0.2.3->fusesoc) (3.0.1)
Requirement already satisfied: jsonschema>=2.5.1 in /usr/lib/python3/dist-packages (from okonomiyaki>=0.16.6->simplesat>=0.8.0->fusesoc) (3.2.0)
Requirement already satisfied: zipfile2>=0.0.12 in /home/gojimmypi/.local/lib/python3.8/site-packages (from okonomiyaki>=0.16.6->simplesat>=0.8.0->fusesoc) (0.0.12)
Requirement already satisfied: MarkupSafe>=2.0 in /home/gojimmypi/.local/lib/python3.8/site-packages (from Jinja2>=2.11.3->edalize>=0.2.3->fusesoc) (2.0.1)
gojimmypi@DESKTOP(WSL): /mnt/c/Windows/System32 ()

0 $  fusesoc library add fusesoc_cores https://github.com/fusesoc/fusesoc-cores
WARNING: The CAPI1 core file description format is deprecated and will be removed in the next major version of FuseSoC. Please port your core files to the CAPI2 format.
Traceback (most recent call last):
  File "/home/gojimmypi/.local/bin/fusesoc", line 8, in <module>
    sys.exit(main())
  File "/home/gojimmypi/.local/lib/python3.8/site-packages/fusesoc/main.py", line 776, in main
    args.func(cm, args)
  File "/home/gojimmypi/.local/lib/python3.8/site-packages/fusesoc/main.py", line 216, in add_library
    config = Config(path="fusesoc.conf")
  File "/home/gojimmypi/.local/lib/python3.8/site-packages/fusesoc/config.py", line 39, in __init__
    with open(path, "a"):
PermissionError: [Errno 13] Permission denied: 'fusesoc.conf'
gojimmypi@DESKTOP(WSL): /mnt/c/Windows/System32 ()

0 $  sudo fusesoc library add fusesoc_cores https://github.com/fusesoc/fusesoc-cores
[sudo] password for gojimmypi:
sudo: fusesoc: command not found
gojimmypi@DESKTOP(WSL): /mnt/c/Windows/System32 ()

Note that changing to the home directory ~, resolves the permission denied problem:

0 $  cd ~
gojimmypi@DESKTOP(WSL): ~ ()

0 $  pwd
/home/gojimmypi
gojimmypi@DESKTOP(WSL): ~ ()

0 $  fusesoc library add fusesoc_cores https://github.com/fusesoc/fusesoc-cores
WARNING: The CAPI1 core file description format is deprecated and will be removed in the next major version of FuseSoC. Please port your core files to the CAPI2 format.
INFO: Cloning library into fusesoc_libraries/fusesoc_cores
Cloning into 'fusesoc_libraries/fusesoc_cores'...
remote: Enumerating objects: 670, done.
remote: Counting objects: 100% (221/221), done.
remote: Compressing objects: 100% (154/154), done.
remote: Total 670 (delta 97), reused 175 (delta 55), pack-reused 449
Receiving objects: 100% (670/670), 144.79 KiB | 1.72 MiB/s, done.
Resolving deltas: 100% (241/241), done.
gojimmypi@DESKTOP(WSL): ~ ()

The problem seems to be when processing arguments to determine the path for the config.

Note my local main.py file line 216 is actually on line 217 of the source for the config = Config(path="fusesoc.conf")

I think the problem is here in the config.py

As at that point, path just contains the text fusesoc.conf, with no path, which also explains the error: I would fully expect things to not be able to write to the Windows system32 directory.

And sure enough, looking in my home directory, there's a new fusesoc.conf file. Is that where it should be?

Probably not, as the FuseSoc Quick start clearly states to create a new directory, but not as clearly indicated in the serv prerequisites, which is where I started.

I created #69 and olofk/fusesoc#536 to help clarify for future new users.

SERV cannot run in fusesoc

Hi, could you help me with this issue? When I tried to run fusesoc run --target=lint serv
this error shows up:
INFO: Preparing ::serv:1.2.1
Traceback (most recent call last):
File "/home/yg9bq/.local/bin/fusesoc", line 8, in
sys.exit(main())
File "/home/yg9bq/.local/lib/python3.6/site-packages/fusesoc/main.py", line 672, in main
fusesoc(args)
File "/home/yg9bq/.local/lib/python3.6/site-packages/fusesoc/main.py", line 662, in fusesoc
args.func(fs, args)
File "/home/yg9bq/.local/lib/python3.6/site-packages/fusesoc/main.py", line 316, in run
edam_file, backend = fs.get_backend(core, flags, args.backendargs)
File "/home/yg9bq/.local/lib/python3.6/site-packages/fusesoc/fusesoc.py", line 171, in get_backend
edam=edam, work_root=work_root, verbose=self.config.verbose
File "/home/yg9bq/.local/lib/python3.6/site-packages/edalize/edatool.py", line 183, in init
loader=PackageLoader(package, "templates"),
File "/home/yg9bq/.local/lib/python3.6/site-packages/jinja2/loaders.py", line 291, in init
assert loader is not None, "A loader was not found for the package."
AssertionError: A loader was not found for the package.

Thanks in advance!!

WSL Does SERV still work with Python 2.7? Version 3.6 not detected

ok, there are a bunch of wonkiness things going on here (WSL, I know I have python 3.x installed, etc.)

But perhaps pip install fusesoc could detect problems and return a more friendly message?

Here's my out-of-box experience this morning using pip install fusesoc:

gojimmypi:~
$ pip install fusesoc
DEPRECATION: Python 2.7 will reach the end of its life on January 1st, 2020. Please upgrade your Python as Python 2.7 won't be maintained after that date. A future version of pip will drop support for Python 2.7.
Collecting fusesoc
  Downloading https://files.pythonhosted.org/packages/cd/4a/e8564fa709494a62f8de718473c76f8fadb6b5ef1b043dea1b547d0c06d0/fusesoc-1.11.0.tar.gz (101kB)
    100% |████████████████████████████████| 102kB 1.7MB/s
    Complete output from command python setup.py egg_info:
    Traceback (most recent call last):
      File "<string>", line 1, in <module>
      File "/tmp/pip-install-dUM5YF/fusesoc/setup.py", line 52, in <module>
        python_requires=">=3.5, <4",
      File "/usr/lib/python2.7/dist-packages/setuptools/__init__.py", line 128, in setup
        _install_setup_requires(attrs)
      File "/usr/lib/python2.7/dist-packages/setuptools/__init__.py", line 123, in _install_setup_requires
        dist.fetch_build_eggs(dist.setup_requires)
      File "/usr/lib/python2.7/dist-packages/setuptools/dist.py", line 513, in fetch_build_eggs
        replace_conflicting=True,
      File "/usr/lib/python2.7/dist-packages/pkg_resources/__init__.py", line 774, in resolve
        replace_conflicting=replace_conflicting
      File "/usr/lib/python2.7/dist-packages/pkg_resources/__init__.py", line 1057, in best_match
        return self.obtain(req, installer)
      File "/usr/lib/python2.7/dist-packages/pkg_resources/__init__.py", line 1069, in obtain
        return installer(requirement)
      File "/usr/lib/python2.7/dist-packages/setuptools/dist.py", line 580, in fetch_build_egg
        return cmd.easy_install(req)
      File "/usr/lib/python2.7/dist-packages/setuptools/command/easy_install.py", line 698, in easy_install
        return self.install_item(spec, dist.location, tmpdir, deps)
      File "/usr/lib/python2.7/dist-packages/setuptools/command/easy_install.py", line 724, in install_item
        dists = self.install_eggs(spec, download, tmpdir)
      File "/usr/lib/python2.7/dist-packages/setuptools/command/easy_install.py", line 909, in install_eggs
        return self.build_and_install(setup_script, setup_base)
      File "/usr/lib/python2.7/dist-packages/setuptools/command/easy_install.py", line 1177, in build_and_install
        self.run_setup(setup_script, setup_base, args)
      File "/usr/lib/python2.7/dist-packages/setuptools/command/easy_install.py", line 1163, in run_setup
        run_setup(setup_script, args)
      File "/usr/lib/python2.7/dist-packages/setuptools/sandbox.py", line 253, in run_setup
        raise
      File "/usr/lib/python2.7/contextlib.py", line 35, in __exit__
        self.gen.throw(type, value, traceback)
      File "/usr/lib/python2.7/dist-packages/setuptools/sandbox.py", line 195, in setup_context
        yield
      File "/usr/lib/python2.7/contextlib.py", line 35, in __exit__
        self.gen.throw(type, value, traceback)
      File "/usr/lib/python2.7/dist-packages/setuptools/sandbox.py", line 166, in save_modules
        saved_exc.resume()
      File "/usr/lib/python2.7/dist-packages/setuptools/sandbox.py", line 141, in resume
        six.reraise(type, exc, self._tb)
      File "/usr/lib/python2.7/dist-packages/setuptools/sandbox.py", line 154, in save_modules
        yield saved
      File "/usr/lib/python2.7/dist-packages/setuptools/sandbox.py", line 195, in setup_context
        yield
      File "/usr/lib/python2.7/dist-packages/setuptools/sandbox.py", line 250, in run_setup
        _execfile(setup_script, ns)
      File "/usr/lib/python2.7/dist-packages/setuptools/sandbox.py", line 44, in _execfile
        code = compile(script, filename, 'exec')
      File "/tmp/easy_install-W_oojy/setuptools_scm-7.0.5/setup.py", line 20
        def scm_version() -> str:
                          ^
    SyntaxError: invalid syntax

    ----------------------------------------
Command "python setup.py egg_info" failed with error code 1 in /tmp/pip-install-dUM5YF/fusesoc/
You are using pip version 19.0.2, however version 20.3.4 is available.
You should consider upgrading via the 'pip install --upgrade pip' command.
gojimmypi:~
$

Here are some version details:

gojimmypi:~
$ lsb_release -a
No LSB modules are available.
Distributor ID: Ubuntu
Description:    Ubuntu 18.04.5 LTS
Release:        18.04
Codename:       bionic
gojimmypi:~
$ python --version
Python 2.7.17
gojimmypi:~
$ python3 --version
Python 3.6.9
gojimmypi:~
$

addi opcode wrong result

Tried to run GCC C compiled code on SERV RISC V.
Seems the addi opcode behaviour is wrong.
assembly code like:
addi sp,sp,-64
or
deadc1b7 lui gp,0xdeadc
eef18193 addi gp,gp,-273 # 0xdeadbeef

result in wrong value in the target register.
Same code on PicoRV32 and on DarkRISCV works fine.

Yosys warning / openlane error on out-of-bound range select in serv_rf_ram.v

Yosys reports a warning on a out-of-bound range select in serv_rf_ram.v.

/content/serv-1.2.1/rtl/serv_rf_ram.v:34: Warning: Range [5:-1] select out of bounds on signal `\i_raddr': Setting 5 LSB bits to undef.

Openlane checkes for that warning and converts it into an error.

[ERROR]: Synthesis failed. Range select out of bounds on some signals. Search for 'out of bounds on signal' in /content/runs/RUN_2023.05.25_06.25.13/logs/synthesis/1-synthesis.log

(Other synthesis solutions also error out on this out-of-bound range select.)

The error is caused by the parameter "width" that defaults to "0", thereby creating a div-by-zero when computing the default parameter "depth", as well as creating the mentioned out-of-bound range select.

module serv_rf_ram
  #(parameter width=0,
    parameter csr_regs=4,
    parameter depth=32*(32+csr_regs)/width)
[...]
   always @(posedge i_clk)
     regzero <= !(|i_raddr[$clog2(depth)-1:5-$clog2(width)]);
[...]

A simple fix would be changing the default of "width" to "2".

\cc @dhaentz1

Yosys error: Signal `\o_par' with invalid width range -1

When Synthesising to an ECP5 the yosys pass fails to parse with this error:

15. Executing Verilog-2005 frontend: /home/greg/projects/DiVA-firmware/hw/serv/rtl/shift_reg.v
Parsing Verilog input from `/home/greg/projects/DiVA-firmware/hw/serv/rtl/shift_reg.v' to AST representation.
Generating RTLIL representation for module `\shift_reg'.
/home/greg/projects/DiVA-firmware/hw/serv/rtl/shift_reg.v:10: ERROR: Signal `\o_par' with invalid width range -1!

I don't know if I want to call this a yosys error. It seems to be doing the right thing, even if these default values are always overwritten with correct values in your design.

Did you see this error when targeting the ice40? or ulx3s?

This can be fixed by providing a default LEN > 0.

diff --git a/rtl/shift_reg.v b/rtl/shift_reg.v
index 64b5ed7..5c4d644 100644
--- a/rtl/shift_reg.v
+++ b/rtl/shift_reg.v
@@ -1,5 +1,5 @@
 module shift_reg
-  #(parameter LEN = 0,
+  #(parameter LEN = 2,
     parameter INIT = 0)
   (
    input wire           clk,

Accessing memory after simulation

Where is the memory file for the simulation output located? I would like to access the changes made to memory location on executing the .hex code in the firmware folder. Is this possible as is, or do I need to make some changes to the run or testbench?

Failing Compliance tests

When running the latest RISC-V Compliance tests using RISCOF framework, three of the privilege tests are failing on SERV.

These are:

• misalign-lh-01
• misalign-lhu-01
• misalign-lw-01

Btw old version of these tests is passing on SERV.

Yosys assertion error on shift_reg

Not sure if this is a yosys bug or a serv bug but I thought you might find it interesting. Yosys read_verilog seems to fail for some reason on shift_reg. Have you seen this before?

Yosys 0.8 (git sha1 UNKNOWN, clang 10.0.0 -fPIC -Os)


yosys> read_verilog shift_reg.v
1. Executing Verilog-2005 frontend.
Parsing Verilog input from `shift_reg.v' to AST representation.
Generating RTLIL representation for module `\shift_reg'.
ERROR: Assert `range_left >= range_right || (range_left == -1 && range_right == 0)' failed in frontends/ast/genrtlil.cc:872.

Yosys Synthesis error : ImportError

I get the following error when trying out to only run synthesis in the icestorm backend by setting pnr to none. I had checked that capi2 exist on my local instance , but still I get this error

workspace sudo fusesoc run --target=tinyfpga_bx servant --pnr=none                  
[sudo] password for nancy: 
INFO: Preparing fusesoc:utils:generators:0.1.3
INFO: Preparing ::serv:0
INFO: Preparing ::wb_common:1.0.3
INFO: Preparing ::wb_ram:1.1
INFO: Preparing ::servant:0
INFO: Generating ::servant-tinyfpga_bx_pll:0
Traceback (most recent call last):
  File "/home/nancy/.cache/fusesoc/fusesoc_utils_generators_0.1.3/icepll.py", line 2, in <module>
    from fusesoc.capi2.generator import Generator
ImportError: No module named fusesoc.capi2.generator

Dockerfile for SERV environment

Hi

I would like to propose we add a docker folder with a Dockerfile in it that contains a Ubuntu based container with all the packages and other assorted goodies needed to build the SERV CPU and run tests. I would be happy to work on a PR for this based on the contents of the CI workflows already checked in.

Is this something that others would consider useful? I would plan to default to checking out the HEAD of the master branch but allow users to pass tags or SHAs into the build command. I think, in time, we could also extent it to include some of the open-source EDA tools needed to build bitstreams for some of the target FPGA boards etc.

Feedback welcome!

No rule to make !!!

How to run the RISC-V Compliance test on verilator as whenever we tried to do so , it generates the above error which indicates that there is something wrong related to the Makefile. I followed the steps from the Readme !!!

trying to follow the Prerequisites instructions

I had to run sudo pip install fusoc, init worked fine, if i run init again, it will fail as directory is not empty.

maiden@Slaven2:~/Projects/serv_ws$ fusesoc library add serv ../serv
WARNING: Parse error. Ignoring file /home/maiden/Projects/serv/serv.core: Unknown item 'generate in section Root'
INFO: Interpreting sync-uri '../serv' as location for local provider.

maiden@Slaven2:~/Projects/serv_ws$  fusesoc run --target=lint serv
WARNING: Parse error. Ignoring file /home/maiden/Projects/serv/serv.core: Unknown item 'generate in section Root'
ERROR: 'serv' or any of its dependencies requires 'serv', but this core was not found

maiden@Slaven2:~/Projects/serv_ws$ fusesoc --version
1.8.4

maiden@Slaven2:~/Projects/serv$ git log 
commit f52eb1931d490dabf75a7f07895a031505b9c1dc (HEAD -> master, origin/master, origin/HEAD)
Author: Olof Kindgren <[email protected]>
Date:   Sat Dec 8 00:16:35 2018 +0100

    Add info about some of serv's shortcomings

Seeking Assistance with SERVANT Integration on Nexys A7 via Eclipse

Hello!
I am excited to share that I have successfully implemented SERVANT on my Nexys A7 FPGA board. My primary objective now is to utilize its UART port for communication. I have prior experience implementing other RISC-V processors and debugging them through Eclipse, and I'm eager to replicate the same process with the SERV CPU.

However, during my exploration of the Zephyr documentation, I encountered some challenges. Specifically, I noticed that there are missing includes in the repository, such as:
#include <drivers/timer/system_timer.h>
and

#include "verilated_vcd_c.h"
#include "Vservant_sim.h"

I am hopeful that you can help clarify this issue and provide guidance for configuring SERVANT via Eclipse. Your assistance in this endeavor would be greatly appreciated.

Thank you in advance for your support.

fusesoc problems with python on Windows - python3 vs python

similar to #83 in WSL, the Windows version of fusesoc seems to not properly detect which version of python to use.

Here in Windows, python is Python version 3.6 and python3 is not defined, causing a fusesoc error:

C:\workspace\myfusesoc>fusesoc run --target=tinyfpga_bx servant
←[1;37mINFO: Preparing fusesoc:utils:generators:0.1.7←[0m
←[1;37mINFO: Downloading fusesoc/fusesoc-generators from github←[0m
←[1;37mINFO: Preparing ::serv:1.1.0←[0m
←[1;37mINFO: Preparing ::servant:1.1.0←[0m
←[1;37mINFO: Generating ::servant-tinyfpga_bx_pll:1.1.0←[0m
Python was not found; run without arguments to install from the Microsoft Store, or disable this shortcut from Settings > Manage App Execution Aliases.
←[1;31mERROR: Setup failed : "python3 C:\Users\gojimmypi\.cache\fusesoc\fusesoc_utils_generators_0.1.7\icepll.py C:\Users\gojimmypi\.cache\fusesoc\generated\servant-tinyfpga_bx_pll_1.1.0\tinyfpga_bx_pll_input.yml" exited with an error code. See stderr for details.←[0m

C:\workspace\myfusesoc>python3 --version
Python was not found; run without arguments to install from the Microsoft Store, or disable this shortcut from Settings > Manage App Execution Aliases.

C:\workspace\myfusesoc>python --version
Python 3.8.1

RV32E configuration

Hi Olof,
Thanks for creating serv.
It's the smallest RISC-V CPU I could find so far.
Small enough that it almost fits on the Speed Tang Nano. (It's just off by 100 or so LUTs.)
I saw that you posted on the RISC-V forums about RV32E for serv. Therefore I was just curious whether you implemented such a configuration.
If not I would be happy to add it if you provide me with some pointers.
I'm using the CPU with LiteX so there is probably some room to save a few LUTs there as well. (Without UART the SoC would fit but that wouldn't be too useful of a system😂).
Best wishes
Martin

Error: Specified --top-module 'servant_sim' was not found in design.

It seems like currently the instructions on how to builder serv/servant from the README.md no longer work.

When I run fusesoc run --target=verilator_tb --setup --build servant I get an error from verilator that it cannot find the toplevel servant_sim. I checked and the file containing that module does not get copied to the build directory.

Unfortunately I do not know enough about fusesoc to find the root cause.

Verilator Lint Fail - UNUSED

The latest checkout (cfb779d) of serv is failing verilator lint. Following is the output:

soumilheble@IH95-LWSTATION:~/Projects/serv$ fusesoc run --target=lint serv
INFO: Preparing ::serv:1.0.2
INFO: Setting up project

INFO: Building simulation model
verilator -f serv_1.0.2.vc -Wall
%Warning-UNUSED: ../src/serv_1.0.2/rtl/serv_params.vh:2:3: Parameter is not used: 'CSR_MSCRATCH'
                                                         : ... In instance serv_rf_top.cpu.decode
    2 |   CSR_MSCRATCH = 2'b00,
      |   ^~~~~~~~~~~~
                 ../src/serv_1.0.2/rtl/serv_decode.v:53:34: ... note: In file included from serv_decode.v
                 ... Use "/* verilator lint_off UNUSED */" and lint_on around source to disable this message.
%Warning-UNUSED: ../src/serv_1.0.2/rtl/serv_params.vh:3:3: Parameter is not used: 'CSR_MTVEC'
                                                         : ... In instance serv_rf_top.cpu.decode
    3 |   CSR_MTVEC    = 2'b01,
      |   ^~~~~~~~~
                 ../src/serv_1.0.2/rtl/serv_decode.v:53:34: ... note: In file included from serv_decode.v
%Warning-UNUSED: ../src/serv_1.0.2/rtl/serv_params.vh:4:3: Parameter is not used: 'CSR_MEPC'
                                                         : ... In instance serv_rf_top.cpu.decode
    4 |   CSR_MEPC     = 2'b10,
      |   ^~~~~~~~
                 ../src/serv_1.0.2/rtl/serv_decode.v:53:34: ... note: In file included from serv_decode.v
%Warning-UNUSED: ../src/serv_1.0.2/rtl/serv_params.vh:5:3: Parameter is not used: 'CSR_MTVAL'
                                                         : ... In instance serv_rf_top.cpu.decode
    5 |   CSR_MTVAL    = 2'b11;
      |   ^~~~~~~~~
                 ../src/serv_1.0.2/rtl/serv_decode.v:53:34: ... note: In file included from serv_decode.v
%Warning-UNUSED: ../src/serv_1.0.2/rtl/serv_params.vh:2:3: Parameter is not used: 'CSR_MSCRATCH'
                                                         : ... In instance serv_rf_top.cpu.rf_if
    2 |   CSR_MSCRATCH = 2'b00,
      |   ^~~~~~~~~~~~
                 ../src/serv_1.0.2/rtl/serv_rf_if.v:45:30: ... note: In file included from serv_rf_if.v
%Warning-UNUSED: ../src/serv_1.0.2/rtl/serv_params.vh:3:3: Parameter is not used: 'CSR_MTVEC'
                                                         : ... In instance serv_rf_top.cpu.rf_if
    3 |   CSR_MTVEC    = 2'b01,
      |   ^~~~~~~~~
                 ../src/serv_1.0.2/rtl/serv_rf_if.v:45:30: ... note: In file included from serv_rf_if.v
%Error: Exiting due to 6 warning(s)
make: *** [Makefile:16: Vserv_rf_top.mk] Error 1
ERROR: Failed to build ::serv:1.0.2 : '['make', '-j', '24', 'Vserv_rf_top.mk']' exited with an error: 2

• serv_decode.v is not using any of the localparams. I haven't looked at the source yet but removing the header should fix the warning.
• serv_rf_if.v is however using 2 of the 4 params.

Potential Fix:

--- a/data/verilator_waiver.vlt
+++ b/data/verilator_waiver.vlt
@@ -2,6 +2,10 @@
 // Bits [1:0] in i_ibus_rdt are not used at all
 lint_off -rule UNUSED -file "*/serv_top.v" -lines 51
 
-//Some bits in the instruction word are not used in serv_decode but it's easier
-//to just send in the whole word than picking out bits
+// Some bits in the instruction word are not used in serv_decode but it's easier
+// to just send in the whole word than picking out bits
 lint_off -rule UNUSED -file "*/serv_decode.v" -lines 6
+
+// CSR localparams (SCRATCH, MTVEC) not used in 
+// serv_rf_if.v
+lint_off -rule UNUSED -file "*/serv_rf_if.v" -lines 45

diff --git a/rtl/serv_decode.v b/rtl/serv_decode.v
index dfd4123..f5846ee 100644
--- a/rtl/serv_decode.v
+++ b/rtl/serv_decode.v
@@ -52,8 +52,6 @@ module serv_decode
    output wire              o_rd_csr_en,
    output wire              o_rd_alu_en);
 
-`include "serv_params.vh"
-
    reg [4:0] opcode;
    reg [2:0] funct3;
    reg               op20;

Tools

fusesoc --version
1.12.0

Verilator 4.200 2021-03-12 rev v4.200-16-gf0d66453

Copyright 2003-2021 by Wilson Snyder.  Verilator is free software; you can
redistribute it and/or modify the Verilator internals under the terms of
either the GNU Lesser General Public License Version 3 or the Perl Artistic
License Version 2.0.

See https://verilator.org for documentation

Summary of configuration:
  Compiled in defaults if not in environment:
    SYSTEMC            = 
    SYSTEMC_ARCH       = 
    SYSTEMC_INCLUDE    = /opt/systemc-2.3.3/include
    SYSTEMC_LIBDIR     = /opt/systemc-2.3.3/lib-linux64
    VERILATOR_ROOT     = /opt/verilator/share/verilator
    SystemC system-wide = 0

Environment:
    MAKE               = 
    PERL               = 
    SYSTEMC            = 
    SYSTEMC_ARCH       = 
    SYSTEMC_INCLUDE    = /opt/systemc-2.3.3/include
    SYSTEMC_LIBDIR     = /opt/systemc-2.3.3/lib-linux64
    VERILATOR_ROOT     = 
    VERILATOR_BIN      = 

problem w/ building reference ?

I'm following the directions precisely. But, I keep getting the same error..

[bwalker@fedora foo]$ export WORKSPACE=$(pwd)
[bwalker@fedora foo]$ fusesoc library add serv https://github.com/olofk/serv
INFO: Cloning library into fusesoc_libraries/serv
Cloning into 'fusesoc_libraries/serv'...
remote: Enumerating objects: 2672, done.
remote: Counting objects: 100% (709/709), done.
remote: Compressing objects: 100% (221/221), done.
remote: Total 2672 (delta 574), reused 488 (delta 488), pack-reused 1963
Receiving objects: 100% (2672/2672), 12.56 MiB | 10.26 MiB/s, done.
Resolving deltas: 100% (1706/1706), done.
[bwalker@fedora foo]$ ls
build  fusesoc.conf  fusesoc_libraries
[bwalker@fedora foo]$ rm -rf build/
[bwalker@fedora foo]$ fusesoc run --target=lint serv
INFO: Preparing ::serv:1.2.1
INFO: Setting up project
INFO: Building simulation model
INFO: Running
[bwalker@fedora foo]$ fusesoc run --target=verilator_tb servant --uart_baudrate=57600 --firmware=$SERV/sw/zephyr_hello.hex
INFO: Preparing ::serv:1.2.1
INFO: Preparing ::servant:1.2.1
verilator -f servant_1.2.1.vc
make -f Vservant_sim.mk
make[1]: Entering directory '/tmp/foo/build/servant_1.2.1/verilator_tb'
g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow      -std=gnu++14 -Os -c -o servant_tb.o src/servant_1.2.1/bench/servant_tb.cpp
g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow      -std=gnu++14 -Os -c -o verilated.o /usr/share/verilator/include/verilated.cpp
g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow      -std=gnu++14 -Os -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp
g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow      -std=gnu++14 -Os -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp
/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vservant_sim.cpp Vservant_sim___024root__DepSet_h03917109__0.cpp Vservant_sim___024root__DepSet_h3f60db9f__0.cpp Vservant_sim_servant__pi1__DepSet_hd3eadecc__0.cpp Vservant_sim_servant__pi1__DepSet_heef88ae2__0.cpp Vservant_sim_servant_ram__pi2__DepSet_h9e6e3df8__0.cpp Vservant_sim__Dpi.cpp Vservant_sim__Trace__0.cpp Vservant_sim___024root__Slow.cpp Vservant_sim___024root__DepSet_h03917109__0__Slow.cpp Vservant_sim___024root__DepSet_h3f60db9f__0__Slow.cpp Vservant_sim_servant_sim__Slow.cpp Vservant_sim_servant_sim__DepSet_h698ba515__0__Slow.cpp Vservant_sim_servant_sim__DepSet_h95578f8b__0__Slow.cpp Vservant_sim_servant__pi1__Slow.cpp Vservant_sim_servant__pi1__DepSet_hd3eadecc__0__Slow.cpp Vservant_sim_servant__pi1__DepSet_heef88ae2__0__Slow.cpp Vservant_sim_servant_ram__pi2__Slow.cpp Vservant_sim_servant_ram__pi2__DepSet_ha27c27ae__0__Slow.cpp Vservant_sim__Syms.cpp Vservant_sim__Trace__0__Slow.cpp > Vservant_sim__ALL.cpp
g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow      -std=gnu++14 -Os -c -o Vservant_sim__ALL.o Vservant_sim__ALL.cpp
echo "" > Vservant_sim__ALL.verilator_deplist.tmp
Archive ar -rcs Vservant_sim__ALL.a Vservant_sim__ALL.o
g++    servant_tb.o verilated.o verilated_dpi.o verilated_vcd_c.o Vservant_sim__ALL.a      -o Vservant_sim
rm Vservant_sim__ALL.verilator_deplist.tmp
make[1]: Leaving directory '/tmp/foo/build/servant_1.2.1/verilator_tb'
Loading RAM from /sw/zephyr_hello.hex
%Warning: /sw/zephyr_hello.hex:0: $readmem file not found
^C
Caught ctrl-c

INFO: ****************************
INFO: ****   FuseSoC aborted  ****
INFO: ****************************

[bwalker@fedora foo]$ 

I never seem to get the "Hello World! service" output..

Zephyr: k_msleep() doesn't work

Hi,

I modified the default hello_world sample program to print the Hello World! message in a loop with a delay as follows:

diff --git a/samples/hello_world/src/main.c b/samples/hello_world/src/main.c
index 2758d75d3f..a0646c789d 100644
--- a/samples/hello_world/src/main.c
+++ b/samples/hello_world/src/main.c
@@ -5,9 +5,13 @@
  */
 
 #include <stdio.h>
+#include <zephyr/kernel.h>
 
 int main(void)
 {
-       printf("Hello World! %s\n", CONFIG_BOARD);
+       while (1) {
+               printf("Hello World! %s\n", CONFIG_BOARD);
+               k_msleep(1);
+       }
        return 0;
 }

However, when I run this, I only get a single Hello World printout (this happens for both Zephyr v3.5.0 and v2.4.0):

[markus@571aaf79e9b4 workspace]$ fusesoc run --target=verilator_tb servant --uart_baudrate=57600 --firmware=hello.hex
INFO: Preparing ::serv:1.2.1
INFO: Preparing ::servant:1.2.1
make: Nothing to be done for 'all'.
Loading RAM from /home/markus/workspace/hello.hex
*** Booting Zephyr OS build zephyr-v3.5.0 ***
Hello World! service
^C
Caught ctrl-c

INFO: ****************************
INFO: ****   FuseSoC aborted  ****
INFO: ****************************

Can you reproduce this / is this a known limitation of servant/service?

Thanks!
Markus

Run on hardware error

I can't generate serv soc for hardware as described in README :

$ cd $SERV/workspace
$ fusesoc run --target=tinyfpga_bx servant
ERROR: Conflicting requirements:
Requirements: 'servant == 0-0' <- 'fusesoc_utils_generators >= 0-0'
    +servant-0-0 was ignored because it depends on missing packages
Requirements: 'servant == 0-0'
    Install command rule (+servant-0-0)

Failed to resolve dependencies for servant

Same for Icebreaker.

SERV to design a Many-Core ASAP7 ASIC

Hi all,
What are the minimum requirements of a SERV core to design a many-core ASIC using ASAP7 predictive PDK? I'm thinking about something like SMP architecture and I'm going to use OpenSoC Fabric as the fabric. I will use ~10mm^2 of die area so I can generate a comparable result with Google's MPWs and SKY130 PDK.

Porting Servant to Terasic's DECA Max 10 board

I just ported it like I did with the SoCKit board, which is the same way as the de0_nano was done.
It take ages to compile and finally complains about no space left on the FPGA. This cannot be possible for just 1 SERV core.
Any ideas of what could happen ?

Error (170011): Design contains 72922 blocks of type combinational node.  However, the device contains only 49760 blocks.
Error (171000): Can't fit design in device

Interrupts not properly masked in Zephyr

The Zephyr Dining Philosophers demo crashes when asserts are enabled. Need to investigate if interrupts are handled correctly on the sw and hw sides. Could be an issue that the mpie bit is not readable and writable from software

fusesoc run --target=verilator_tb servant --uart_baudrate=55600 --memsize=65536 --firmware zephyr35_phil.hex 
INFO: Preparing ::serv:1.2.1
INFO: Preparing ::servant:1.2.1
make: Nothing to be done for 'all'.
Loading RAM from /home/olof/projects/serv/workspace/zephyr35_phil.hex
*** Booting Zephyr OS build zephyr-v3.5.0 ***
Demo Description
----------------
An implementation of a solution to the Dining Philosophers
problem (a classic multi-thread synchronization problem).
This particular implementation demonstrates the usage of multiple
preemptible and cooperative threads of differing priorities, as
well as dynamic mutexes and thread sleeping.




Philosopher 0 [C:-2]   EATING  [  02 ms ]  
ASSERTION FAIL [arch_irq_unlocked(key) || _kernel.cpus[0].current->base.thread_state & (((1UL << (0))) | ((1UL << (3))))] @ WEST_TOPDIR/zephyr/kernel/include/kswap.h:02
	Context switching while holding lock!
^C
Caught ctrl-c

INFO: ****************************
INFO: ****   FuseSoC aborted  ****

Using wb_intercon for servant

Why did you not use wb_intercon for creating the the mux and arbiter for the RAM/ROM? I was going to use wb_intercon and serv for a project.

Possible incorrect `ret` behaviour using default `serv_rf_top` instantiation

I have a simple instantiation of the serv_rf_top module connected directly to a block RAM that doubles as firmware ROM and a small RAM. When running a test program, the CPU appears to execute correctly until it reaches a ret instruction and attempts to load the x1 register to read the return address. When it does so, it appears to actually load x1 * 2, resulting in a bogus PC address and undefined behaviour.

The relevant instructions of the minimal test case executing below are:

01000010 <func0(unsigned long, unsigned long)>:
 1000010:       00050793                mv      a5,a0
 1000014:       00008067                ret
...
void main() {
 100019c:       e75ff0ef                jal     ra,1000010 <func0(unsigned long, unsigned long)>
 10001a0:       fff00793                li      a5,-1

Checking the trace as we execute instruction 0x100019c, we can see on the formal interface that we are correctly writing the return address 0x10001a0 to the link register x1.

However, a few instructions later at 0x1000014, we then read x1 back but this time we get a different result, 0x02000340, which happens to be our expected x1 register value but left shifted by one.

Is this a user error on my part? Is there any other information that would be useful to debug this behaviour? Unfortunately I cannot directly share the testbench I am using to replicate this error, but if necessary could create a SSCCE.

I am using serv code from commit e59fe53, and testing using verilator 4.100

Zephyr dining-philosophers-sample > region `RAM' overflowed

I tried to compile the Zephyr dining-philosophers-sample without success.
Below I explain how I did it. Please let me know how did you success on compiling it.

Procedure:
Followed instructions detailed in "Zephyr support" from Readme.md
cd zephyr/samples/philosophers
west build -b service

/home/jordi/bin/zephyr-sdk-0.12.1/riscv64-zephyr-elf/bin/../lib/gcc/riscv64-zephyr-elf/10.2.0/../../../../riscv64-zephyr-elf/bin/ld: zephyr/zephyr_prebuilt.elf section `noinit' will not fit in region `RAM'
/home/jordi/bin/zephyr-sdk-0.12.1/riscv64-zephyr-elf/bin/../lib/gcc/riscv64-zephyr-elf/10.2.0/../../../../riscv64-zephyr-elf/bin/ld: region `RAM' overflowed by 3936 bytes
Memory region         Used Size  Region Size  %age Used
             RAM:       36704 B        32 KB    112.01%
        IDT_LIST:          25 B         2 KB      1.22%
collect2: error: ld returned 1 exit status
ninja: build stopped: subcommand failed.
FATAL ERROR: command exited with status 1: /usr/bin/cmake --build /home/jordi/bin/fusesoc/zephyr/samples/philosophers/build

Zephyr hello world in Alhambra board

Hi,

I am trying to run the example in Alhambra board, that contains a 12MHz clock and a iCE40HX4K fpga. I have managed to synthesize and upload the example. But, once I open a minicom session and reset the board, it reads some garbage:

��|�������p

I believe that is due to the clock frequency, as you mention in the Readme, as the uart_tx in bitbanged, could be some sync or speed issue? Any idea how can I fix it?

Thanks in advance for the help!

Various command line options not working: --firmware, --uart_baudrate

I'm trying to follow the simple instructions on get the award winning serv(tm) running on my machine (Ubuntu 16.04), but I'm running into issues.

tom@thinkcenter:~/projects/serv/workspace$ fusesoc run --target=verilator_tb servant --uart_baudrate=57600 --firmware=$SERV/serv/sw/zephyr_hello.hex
INFO: Preparing ::serv:1.0.0-r1
INFO: Preparing ::servant:1.0.0
usage: fusesoc run servant_1.0.0 [-h] [--RISCV_FORMAL] [--SERV_CLEAR_RAM]
                                 [--mode MODE] [--cli_parser CLI_PARSER]
                                 [--libs LIBS]
                                 [--verilator_options VERILATOR_OPTIONS]
                                 [--make_options MAKE_OPTIONS]
                                 [--run_options RUN_OPTIONS]
fusesoc run servant_1.0.0: error: unrecognized arguments: --uart_baudrate=57600 --firmware=/home/tom/projects/serv/serv/sw/zephyr_hello.hex
tom@thinkcenter:~/projects/serv/workspace$ 

When I remove the --uart_baudrate option, it will barf on the --firmware option just the same.

I have installed all the Python options with pip3 instead of pip.

Any suggestions on how to proceed?

Tom

Compressed instruction support for SERV

I would like to work on this task, how can I get in contact with you?

background info

is there any good documentation/papers that you can refer to? or is it best to just "read the code",
google gave me this: http://fpga-guru.com/files/supercn.pdf

Broken video links

The video links in README.md for "introduction to SERV" and "SERV : RISC-V for a fistful of gates" seems to be broken (assuming diode.zone host is down).

%Warning: /sw/zephyr_hello.hex:0: $readmem file not found

hello.
first of all, thanks for sharing the SERV project.
facing problem :
Command : fusesoc run --target=verilator_tb servant --uart_baudrate=57600 --firmware=$SERV/sw/zephyr_hello.hex
Result : Loading RAM from /sw/zephyr_phil.hex
%Warning: /sw/zephyr_phil.hex:0: $readmem file not found

How can i solve this Warning?

i think, it's because this warning ,I dont get [***** Booting Zephyr OS zephyr-v1.14.1-4-gc7c2d62513fe *****
Hello World! service]

thanks.

fusesoc library add does not detect duplicates

My fusesoc library list seemed somewhat short. Ok, I didn't know how long it should be, I suppose I was expecting to see a list of boards.

Running fusesoc library add as noted in the instructions just added a duplicate fusesoc-cores for me. (see below)

Perhaps it would be good if it stated [name] was already installed?

C:\workspace\myfusesoc>fusesoc library list
Name          : Location                        : Sync type : Sync URI                                 : Auto sync
fusesoc_cores : fusesoc_libraries\fusesoc_cores : git       : https://github.com/fusesoc/fusesoc-cores : y
serv          : fusesoc_libraries\serv          : git       : https://github.com/olofk/serv            : y

C:\workspace\myfusesoc>fusesoc library add fusesoc-cores https://github.com/fusesoc/fusesoc-cores
←[1;37mINFO: Cloning library into fusesoc_libraries\fusesoc-cores←[0m
Cloning into 'fusesoc_libraries\fusesoc-cores'...
remote: Enumerating objects: 678, done.
remote: Counting objects: 100% (101/101), done.
remote: Compressing objects: 100% (26/26), done.
Receiving objects:  89% (604
Receiving objects: 100% (678/678), 141.02 KiB | 2.61 MiB/s, done.
Resolving deltas: 100% (265/265), done.

C:\workspace\myfusesoc>fusesoc library list
Name          : Location                        : Sync type : Sync URI                                 : Auto sync
fusesoc_cores : fusesoc_libraries\fusesoc_cores : git       : https://github.com/fusesoc/fusesoc-cores : y
serv          : fusesoc_libraries\serv          : git       : https://github.com/olofk/serv            : y
fusesoc-cores : fusesoc_libraries\fusesoc-cores : git       : https://github.com/fusesoc/fusesoc-cores : y