syntacore/scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

SCR1 RISC-V Core

SCR1 is an open-source and free to use RISC-V compatible MCU-class core, designed and maintained by Syntacore. It is industry-grade and silicon-proven (including full-wafer production), works out of the box in all major EDA flows and Verilator, and comes with extensive collateral and documentation.

Key features

• Open sourced under SHL-license (see LICENSE file) - unrestricted commercial use allowed
• RV32I or RV32E ISA base + optional RVM and RVC standard extensions
• Machine privilege mode only
• 2 to 4 stage pipeline
• Optional Integrated Programmable Interrupt Controller with 16 IRQ lines
• Optional RISC-V Debug subsystem with JTAG interface
• Optional on-chip Tightly-Coupled Memory
• 32-bit AXI4/AHB-Lite external interface
• Written in SystemVerilog
• Optimized for area and power
• 3 predefined recommended configurations
• A number of fine-tuning options for custom configuration
• Verification suite provided
• Extensive documentation

For more information on core architecture, see SCR1 External Architecture Specification.

For more information on project usage, see SCR1 User Manual.

Repository contents

Folder	Description
dependencies	Dependent submodules
├─ riscv-tests	Common source files for RISC-V ISA tests
├─ riscv-compliance	Common source files for RISC-V Compliance tests
└─ coremark	Common source files for EEMBC's CoreMark® benchmark
docs	SCR1 documentation
├─ scr1_eas.pdf	SCR1 External Architecture Specification
└─ scr1_um.pdf	SCR1 User Manual
sim	Tests and scripts for simulation
├─ tests/common	Common source files for tests
├─ tests/riscv_isa	RISC-V ISA tests platform specific source files
├─ tests/riscv_compliance	RISC-V Compliance platform specific source files
├─ tests/benchmarks/dhrystone21	Dhrystone 2.1 benchmark source files
├─ tests/benchmarks/coremark	EEMBC's CoreMark® benchmark platform specific source files
├─ tests/isr_sample	Sample program "Interrupt Service Routine"
├─ tests/hello	Sample program "Hello"
└─ verilator_wrap	Wrappers for Verilator simulation
src	SCR1 RTL source and testbench files
├─ includes	Header files
├─ core	Core top source files
├─ top	Cluster source files
└─ tb	Testbench files

SCR1 source file lists

SCR1 source file lists of SCR1 can be found in ./src:

• core.files - all synthesized file sources of the SCR1 core
• ahb_top.files - synthesized file sources of AHB cluster
• axi_top.files - synthesized file sources of AXI cluster
• ahb_tb.files - testbench file sources for AHB cluster (for simulation only)
• axi_tb.files - testbench file sources for AXI cluster (for simulation only)

Library with header files to include is ./src/includes/

Simulation quick start guide

The project contains testbenches, test sources and scripts to quickly start the SCR1 simulation. Before starting the simulation, make sure you have:

• installed RISC-V GCC toolchain,
• installed one of the supported simulators,
• initialized submodules with test sources.

Requirements

Operating system

GCC toolchain and make-scripts are supported by most popular Linux-like operating systems.

To run from Windows you can use an additional compatibility layer, such as WSL or Cygwin.

RISC-V GCC toolchain

RISC-V GCC toolchain is required to compile the software. You can use pre-built binaries or build the toolchain from scratch.

Using pre-built binary tools

Pre-built RISC-V GCC toolchain with support for all SCR1 architectural configurations is available for download from http://syntacore.com/page/products/sw-tools.

1. Download the archive for your platform.
2. Extract the archive to preferred directory <GCC_INSTALL_PATH>.
3. Add the <GCC_INSTALL_PATH>/bin folder to the $PATH environment variable:

    export PATH=<GCC_INSTALL_PATH>/bin:$PATH

Building tools from source

You can build the RISC-V GCC toolchain from sources, stored in official repo https://github.com/riscv/riscv-gnu-toolchain

Instructions on how to prepare and build the toolchain can be found on https://github.com/riscv/riscv-gnu-toolchain/blob/master/README.md

We recommend using the multilib compiler. Please note that RV32IC, RV32E, RV32EM, RV32EMC, RV32EC architectural configurations are not included in the compiler by default. If you plan to use them, you will need to include the appropriate libraries by yourself before building.

After the building, be sure to add the <GCC_INSTALL_PATH>/bin folder to the $PATH environment variable

HDL simulators

Currently supported simulators:

• Verilator (last verified version: v5.014)
• Mentor Graphics ModelSim (last verified version: INTEL FPGA STARTER EDITION 2020.1)
• Synopsys VCS (last verified version: S-2021.09-1)
• Cadence NCSim (last verified version: 22.09-s004)

Please note that RTL simulator executables should be in your $PATH variable.

Tests preparation

The simulation package includes the following tests:

• hello - "Hello" sample program
• isr_sample - "Interrupt Service Routine" sample program
• riscv_isa - RISC-V ISA tests (submodule)
• riscv_compliance - RISC-V Compliance tests (submodule)
• dhrystone21 - Dhrystone 2.1 benchmark
• coremark - EEMBC's CoreMark® benchmark (submodule)

After the main SCR1 repository has been cloned execute the following command:

    git submodule update --init --recursive

This command will initialized submodules with test sources.

Running simulation

To build RTL, compile and run tests from the repo root folder you have to call Makefile. By default, you may simply call Makefile without any parameters:

    make

In this case simulation will run on Verilator with following parameters: CFG=MAX BUS=AHB TRACE=0 TARGETS="hello isr_sample riscv_isa riscv_compliance dhrystone21 coremark".

Makefile supports:

• choice of simulator - run_<SIMULATOR> = <run_vcs, run_modelsim, run_ncsim, run_verilator, run_verilator_wf>
• selection of external interface - BUS = <AHB, AXI>,
• configuration setup - CFG = <MAX, BASE, MIN, CUSTOM>,
• parameters for CUSTOM configuration - ARCH = <IMC, IC, IM, I, EMC, EM, EC, E>, VECT_IRQ = <0, 1>, IPIC = <0, 1>, TCM = <0, 1>
• tests subset to run - TARGETS = <hello, isr_sample, riscv_isa, riscv_compliance, dhrystone21, coremark>
• enabling tracelog - TRACE = <0, 1>
• and any additional options to pass to the simulator - SIM_BUILD_OPTS.

Examples:

    make run_verilator_wf CFG=MAX BUS=AXI TARGETS="riscv_isa riscv_compliance" TRACE=1
    make run_vcs CFG=BASE BUS=AHB TARGETS="dhrystone21 coremark" SIM_BUILD_OPTS="-gui"
    make run_modelsim CFG=CUSTOM BUS=AXI ARCH=I VECT_IRQ=1 IPIC=1 TCM=0 TARGETS=isr_sample

Build and run parameters can be configured in the ./Makefile.

After all the tests have finished, the results can be found in build/<SIM_CFG>/test_results.txt.

IMPORTANT: To ensure correct rebuild, please clean build directory between simulation runs:

    make clean

Please refer to the "Simulation environment" chapter of the SCR1 User Manual for more information on setting up a simulation run.

SCR1 SDKs

FPGA-based SDKs are available at the https://github.com/syntacore/scr1-sdk.

Repo contains:

• Pre-build images and open designs for several standard FPGAs boards:
  • Digilent Arty (Xilinx)
  • Digilent Nexys 4 DDR (Xilinx)
  • Arria V GX Starter (Intel)
  • Terasic DE10-Lite (Intel)
• Software package:
  • Bootloader
  • Zephyr RTOS
  • Tests\SW samples
• User Guides for SDKs and tools

Contacts

Report an issue: https://github.com/syntacore/scr1/issues

Ask a question: [email protected]

scr1's Issues

Are there any big modification for correct synthesis results?

Hello,

I am trying to synthesize and tap-out a prototype chip using scr1. Many thanks to the nice work and kind continuous update!

Since I am cloning scr1 half year ago, I am wondering if there's any important updates for correct synthsized results. Because I stuck at unknown standard delay format annotation failure after generating .sdf files using dc_shell and run gate-level simulation using irun.

Many Thanks!

Best Regards,
Yun-Chen Lo

Where can I get getdouble and printdoubleF function?

I find the sc_print.c missing getdouble and printdoubleF function. Can you give me a complete sc_print.c file?
Thanks!

Verilator timing required?

Hello,

Just wanted to point out that the quickstart with Verilator is not working.

Cloning the repository and doing:

make run_verilator CFG=MAX BUS=AHB TRACE=0 TARGETS="hello"

Gives out a error that delayed assignments are used.
Particularly one block of code is an issue:

scr1/src/tb/scr1_top_tb_ahb.sv

Lines 261 to 272 in d8ba8e5

	`ifdef SCR1_DBG_EN
	initial begin
	trst_n = 1'b0;
	tck = 1'b0;
	tdi = 1'b0;
	#900ns trst_n = 1'b1;
	#500ns tms = 1'b1;
	#800ns tms = 1'b0;
	#500ns trst_n = 1'b0;
	#100ns tms = 1'b1;
	end
	`endif // SCR1_DBG_EN

Similar for AXI testbench.
I didn't analyze what was the intended function behind it, but you either forgot `ifndef VERILATOR around it or to disable the SCR1_DBG_EN for verilator simulation.

Other option is to bump the Verilator version to > 5.0 and use the --timing feature.
For this you need also C++ compiler with C++20 (coroutines) support, but I tested it and it works.

The behavior of Stepping through DCSR.step and DMCONTROL.resumereq

Hi,

I was wondering why do I have to Halt the hart again after a step and before the next step? I have tested that the hart must be halt (DMCONTROL.haltreq) again after a resume request (DMCONTROL.resumereq), otherwise the next step (resume request) would not work.

To my understanding on "riscv-debug-release.pdf, section 'Appendix B.5'", should not the hart be halt automatically after the resume request?

Thank you. :-)

AXI Interconnect problems

Hi,

I would like to try adding an axi_interconnect module between the SCR1 and memory for simulation. Additionally, if possible, I would also like to add some simple slaves to the axi to form a basic SoC.
Originally, in scr1_top_tb_axi, the SCR1 and memory were directly connected. However, I encountered some difficulties when trying to add an axi_interconnect module between SCR1 and memory. I modified scr1_top_tb_axi and added the axi module. The command I am using is: make run_vcs CFG=CUSTOM BUS=AXI ARCH=I VECT_IRQ=0 IPIC=0 TCM=0 TARGETS="hello". When I set the BASE_ADDR to 0x200 (the starting address of SCR1), an 'not aligned' error occurs.

Furthermore, I noticed descriptions related to 'addr' in the scr1_imem_router.sv and scr1_dmem_router.sv files. Therefore, setting the BASE_ADDR to 0x10000 and BASE_ADDR to 0x480000 (which are connected to this parameter in scr1_top_axi) also did not work properly.

I would like to ask for advice on how to correctly set the memory address. Thank you very much for your help!

Additional information: The axi interconnect module I am using is from the following URL:
https://github.com/alexforencich/verilog-axi
If you have any recommendations on which module to use, please let me know. Thank you so much.

Best regards,
Jui

Unable to print variables using sc_printf

#include "sc_print.h"
#include<stdlib.h>
int main()
{
sc_printf("Entering Pointer Bounds Check!\n");
int* ptr = malloc(10 * sizeof(int));
for(int i = 0; i < 10; i++){
ptr[i] = i;
}
int x = ptr[100];
sc_printf("X : %d", x); // Leads to an error _sbrk_r gcc undefined
sc_printf("Bounds Check Complete!\n");
return 0;
}

In the above code, the sc_printf("%d", var_name) shows errors and doesn't generate the result.

cannot generate random number on scr1 with pre-build binary tool

Hi,
I'm trying to run simple C code on scr1, but failed to generate random number.
I used 'rand()' in the C code and compiled it with the pre-build binary tool which was downloaded from http://syntacore.com/page/products/sw-tools. (in Linux)
But the 'rand()' always returned zero value.

AHB Interconnect Integration

Hi @wsnyder @aka-sps @ar-sc @dp-sc @eb-sc ,
I am trying to integrate an AHB Interconnect to the SCR1 core in my SoC. I see that the SCR1 has an IMEM and DMEM interface but no standard bus interface. So, how would someone go about integrating the SCR1 core to the bus? And I am assuming the IMEM and DMEM interface is a point-to-point connection in the SCR1 core.
Please help. Thanks

Debug with Segger J-link

As described on page 13 of below document. J-link can work with SCR1.
https://content.riscv.org/wp-content/uploads/2018/07/Shanghai-0925_AM_Syntacore_SCRx_SHA_day.pdf
But my test failed , can't halt the cpu, connection failed.

The error message in Ozone 2.61c
"JTAG chain detection found 1 devices:
#0 Id:0xDEB01001, IRLen: 04, Unknown device
CPU-TAP not found in JTAG chain"

Per-instance customization via module parameters

It looks like customization of the core configuration is all done via preprocessor macros instead of module instance parameters. The problem with this is that it's not possible to include multiple instances of the core in a design with different settings - for instance, maybe a design needs a couple of smaller cores with several features disabled, in addition to a higher-performance core with a different set of features enabled. It seems like most of the preprocessor macros can probably be replaced with module parameters, which would make the core significantly more flexible.

any plan to integrate the axi interface to the sram?

you are using AHB-lite to connect the sram,
any plan to integrate the axi bus instead of AHB?

Which files are need to be synthesized?

Dear Sir,

I am trying to synthesize scr1 using dc_shell.
As all files are written in system verilog, I am wondering which files need to be synthesized?

Currently I put all files list in src/axi_top.files and src/core.files to analyze command in dc_shell

Thank you,
Yun-Chen Lo

Verilator now supports implication in assertions, you should be able to remove ifdefs

Hi,

I have addd support for the implication operators in Verilator. You should now be able to remove many ifdefs from the RTL code if you have Verilator 4.102.

Best Regards
Peter

How does it work for sc_print to print words in terminal when running HDL simulator?

Hi,

I have been exploring how to compile sc_print.c into a hex file using the RISCV toolchain and then load it into the memory model using the system call $readmemh. However, I am curious about how the print text is displayed on the terminal when using an HDL simulator (e.g., vcs).

I have looked through scr1_top_tb_runtests.sv and other related files but haven't been able to find a $display function or any reference to how SC_SIM_OUTPORT (0xf0000000) is handled. Could you please provide some insights or guidance on how this process works?

Thank you very much for your time and assistance. I greatly appreciate any help you can offer.

Best regards,
WeiPo

Non atomicity of traps on SCR1 core ?

Hello SCR1 team,

I have doubts about trap atomicity on SCR1 core, that is:
I am able to raise exceptions on incorrect bus transactions even though MSTATUS = 0x00001800 and MIE = 0x0
Also, after reset MSTATUS=0x00001880, that is mstatus.mpie = '1' (machine previous interrupt enable)
Why is bit 7 '1'? shouldn't it be '0' after reset ?

As far as I understand the RISC-V Instruction Set Manual / Volume II: Privileged Architecture (but I may be wrong) traps are allowed in machine mode only when mstatus.mie = '1'

Therefore a trap in a trap can be raised leading to an infinite loop, where having disabled trap (in the trap handler for example) should enforce atomicity of traps.

I have attached a VCD file where I can raise a trap on bus error when traps have not been enabled, and even trap in a trap infinite loop.

I may be wrong in my analysis, in this case, how can I enforce atomicity of trap in trap handlers ?
If it is effectively a hardware bug, is there a quick patch that I can very quickly apply before synthesis ?

Thank you very much,
Kind regards

Jean-Marc
scr1-iaf.vcd.gz
trace_csr_0.log

Endless loop on CFG=MIN

Hello, I've just found a bug:

Running command
$ make run_verilator_wf CFG=MIN TARGETS="riscv_isa riscv_compliance"
return never ends loop.
Last line i can see in terminal is:

printf "$(cat /home/$USER/scr1/build/verilator_wf_AHB_MIN_ec_IPIC_0_TCM_1_VIRQ_0_TRACE_0/test_results.txt) \n"
scr1_top_tb_ahb

Loop continue about 5-6 mins until I have no free space left on my host.
As the result we got extremely large folder:

$ du -h | grep TRACE_0$
68G	./verilator_wf_AHB_MIN_ec_IPIC_0_TCM_1_VIRQ_0_TRACE_0

Verilator version: Verilator 4.213 devel rev v4.212-25-g08c8b0d7
gcc from http://syntacore.com/page/products/sw-tools
Linux version 5.11.0-37-generic (buildd@lcy01-amd64-021) (gcc (Ubuntu 9.3.0-17ubuntu1 20.04) 9.3.0, GNU ld (GNU Binutils for Ubuntu) 2.34) #41 20.04.2-Ubuntu SMP Fri Sep 24 09:06:38 UTC 2021

Verilator issue while running make

Hello,
I have a problem running make command and below is the terminal output after make command.
Do you have any idea to fix this issue?
I tried to check the error line of "scr1_pipe_csr.sv:1094" and I think it is related to some SystemVerilog assertion (implication construct) but I didn't know why this error comes out.

Any help will be appreciated

Terminal Output - Ubuntu 18.04
/**/
make -f Vscr1_top_tb_axi.mk;
%Error: /home/hossam/RISC-V_Cores/syntacore/scr1/src/core/pipeline/scr1_pipe_csr.sv:1094:12: syntax error, unexpected |=>, expecting ')'
1094 | e_mret |=> ($stable(csr_mepc_ff) & $stable(csr_mtval_ff))
| ^~~
%Error: /home/hossam/RISC-V_Cores/syntacore/scr1/src/core/pipeline/scr1_pipe_csr.sv:1100:5: syntax error, unexpected |=>, expecting ')'
1100 | |=> ($stable(csr_mepc_ff) & (exu2csr_pc_curr_i != csr_mepc))
| ^~~
%Error: /home/hossam/RISC-V_Cores/syntacore/scr1/src/core/pipeline/scr1_pipe_csr.sv:1109:7: syntax error, unexpected |=>, expecting ')'
1109 | ) |=>
| ^~~
%Error: /home/hossam/RISC-V_Cores/syntacore/scr1/src/core/pipeline/scr1_pipe_csr.sv:1126:30: syntax error, unexpected |=>, expecting ')'
1126 | csr2exu_mstatus_mie_up_o |=> ~csr2exu_mstatus_mie_up_o
| ^~~
%Error: /home/hossam/RISC-V_Cores/syntacore/scr1/src/core/pipeline/scr1_pipe_csr.sv:1140:24: syntax error, unexpected |=>, expecting ')'
1140 | (~|csr_mcycle_upd) |=>
| ^~~
%Error: /home/hossam/RISC-V_Cores/syntacore/scr1/src/core/pipeline/scr1_pipe_csr.sv:1150:53: syntax error, unexpected |=>, expecting ')'
1150 | (exu2csr_instret_no_exc_i & ~|csr_minstret_upd) |=>
| ^~~
%Error: /home/hossam/RISC-V_Cores/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv:688:63: syntax error, unexpected |=>, expecting ')'
688 | (mdu_fsm_idle & (~exu2ialu_rvm_cmd_vd_i | ~mdu_iter_req)) |=> mdu_fsm_idle
| ^~~
%Error: /home/hossam/RISC-V_Cores/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv:693:59: syntax error, unexpected |=>, expecting ')'
693 | (mdu_fsm_idle & exu2ialu_rvm_cmd_vd_i & mdu_iter_req) |=> mdu_fsm_iter
| ^~~
%Error: /home/hossam/RISC-V_Cores/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv:698:36: syntax error, unexpected |=>, expecting ')'
698 | (mdu_fsm_iter & ~mdu_iter_rdy) |=> mdu_fsm_iter
| ^~~
%Error: /home/hossam/RISC-V_Cores/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv:703:51: syntax error, unexpected |=>, expecting ')'
703 | (mdu_fsm_iter & mdu_iter_rdy & ~mdu_corr_req) |=> mdu_fsm_idle
| ^~~
%Error: /home/hossam/RISC-V_Cores/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv:708:50: syntax error, unexpected |=>, expecting ')'
708 | (mdu_fsm_iter & mdu_iter_rdy & mdu_corr_req) |=> mdu_fsm_corr
| ^~~
%Error: /home/hossam/RISC-V_Cores/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv:713:18: syntax error, unexpected |=>, expecting ')'
713 | mdu_fsm_corr |=> mdu_fsm_idle
| ^~~
%Error: /home/hossam/RISC-V_Cores/syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv:783:28: syntax error, unexpected |=>, expecting ')'
783 | ~imem_resp_discard_req |=> ~(imem_resp_discard_cnt == SCR1_TXN_CNT_W'('1))
| ^~~
%Error: /home/hossam/RISC-V_Cores/syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv:800:69: syntax error, unexpected |=>, expecting ')'
800 | (imem_resp_er & ~imem_resp_discard_req & ~exu2ifu_pc_new_req_i) |=>
| ^~~
%Error: /home/hossam/RISC-V_Cores/syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv:806:26: syntax error, unexpected |=>, expecting ')'
806 | exu2ifu_pc_new_req_i |=> q_is_empty
| ^~~
%Error: /home/hossam/RISC-V_Cores/syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv:816:27: syntax error, unexpected |=>, expecting ')'
816 | pipe2ifu_stop_fetch_i |=> (ifu_fsm_curr == SCR1_IFU_FSM_IDLE)
| ^~~
%Error: Exiting due to 16 error(s)
/bin/sh: line 23: cd: verilator: No such file or directory
make[2]: Entering directory '/home/hossam/RISC-V_Cores/syntacore/scr1/build/verilator_wf_AXI_MAX_imc_IPIC_1_TCM_1_VIRQ_1_TRACE_0'
make[2]: Vscr1_top_tb_axi.mk: No such file or directory
make[2]: *** No rule to make target 'Vscr1_top_tb_axi.mk'. Stop.
make[2]: Leaving directory '/home/hossam/RISC-V_Cores/syntacore/scr1/build/verilator_wf_AXI_MAX_imc_IPIC_1_TCM_1_VIRQ_1_TRACE_0'
Makefile:102: recipe for target 'build_verilator_wf' failed
make[1]: *** [build_verilator_wf] Error 2
make[1]: Leaving directory '/home/hossam/RISC-V_Cores/syntacore/scr1/sim'
Makefile:275: recipe for target 'run_verilator_wf' failed
make: *** [run_verilator_wf] Error 2

Thanks in advance

Error 'make tests' fails

I have followed the instructions for isntallation and getting started but face an issue with building tests. This is my first time looking at RISC-V based core and toolchains etc, so please be kind :)

I have the most recent master (d8ba8e5) and sc-dt_2022.12-sp1 release of pre-built tools.

When running make tests I get the following error

cameron@magpie:~/projects/syntacore/scr1$ make tests
make -C /home/cameron/projects/syntacore/scr1/sim/tests/riscv_isa ARCH=imc
make[1]: Entering directory '/home/cameron/projects/syntacore/scr1/sim/tests/riscv_isa'
riscv64-unknown-elf-gcc -c /home/cameron/projects/syntacore/scr1/sim/tests/riscv_isa/../../../dependencies/riscv-tests/isa/rv32ui/fence_i.S -I/home/cameron/projects/syntacore/scr1/sim/tests/common -I/home/cameron/projects/syntacore/scr1/sim/tests/riscv_isa -DASM -Wa,-march=rv32imfc -march=rv32imfc -mabi=ilp32f -D__riscv_xlen=32 -o /home/cameron/projects/syntacore/scr1/build/tests_AHB_MAX_imc_IPIC_1_TCM_1_VIRQ_1_TRACE_0/riscv_objs/fence_i.o
/home/cameron/projects/syntacore/scr1/sim/tests/riscv_isa/../../../dependencies/riscv-tests/isa/rv32ui/../rv64ui/fence_i.S: Assembler messages:
/home/cameron/projects/syntacore/scr1/sim/tests/riscv_isa/../../../dependencies/riscv-tests/isa/rv32ui/../rv64ui/fence_i.S:24: Error: unrecognized opcode `fence.i'
/home/cameron/projects/syntacore/scr1/sim/tests/riscv_isa/../../../dependencies/riscv-tests/isa/rv32ui/../rv64ui/fence_i.S:37: Error: unrecognized opcode `fence.i'
make[1]: *** [Makefile:33: /home/cameron/projects/syntacore/scr1/build/tests_AHB_MAX_imc_IPIC_1_TCM_1_VIRQ_1_TRACE_0/riscv_objs/fence_i.o] Error 1
make[1]: Leaving directory '/home/cameron/projects/syntacore/scr1/sim/tests/riscv_isa'
make: *** [Makefile:219: riscv_isa] Error 2

After a little investigation it seems to be a related to binutils v2.38 or newer.

From https://www.mail-archive.com/[email protected]/msg40386.html

From version 2.38, binutils default to ISA spec version 20191213. This
means that the csr read/write (csrr*/csrw*) instructions and fence.i
instruction has separated from the I extension, become two standalone
extensions: Zicsr and Zifencei.

The fix is to specify those extensions explicitly in -march. However as
older binutils version do not support this, we first need to detect
that.

Of course it could be more complicated.

Make error

%Error: scr1/src/core/pipeline/scr1_pipe_csr.sv:1096: syntax error, unexpected |=>, expecting ')'                     e_mret |=> ($stable(csr_mepc_ff) & $stable(csr_mtval_ff))              ^~~                                                  
%Error: scr1/src/core/pipeline/scr1_pipe_csr.sv:1096: Unsupported or unknown PLI call: $stable                        e_mret |=> ($stable(csr_mepc_ff) & $stable(csr_mtval_ff))                   ^~~~~~~                                         
%Error:  scr1/src/core/pipeline/scr1_pipe_csr.sv:1096: Unsupported or unknown PLI call: $stable                        e_mret |=> ($stable(csr_mepc_ff) & $stable(csr_mtval_ff))                                          ^~~~~~~                 
 %Error: scr1/src/core/pipeline/scr1_pipe_csr.sv:1102: syntax error, unexpected |=>, expecting ')'                     |=> ($stable(csr_mepc_ff) & (exu2csr_pc_curr_i != csr_mepc))    ^~~                                                         
%Error: scr1/src/core/pipeline/scr1_pipe_csr.sv:1102: Unsupported or unknown PLI call: $stable                        |=> ($stable(csr_mepc_ff) & (exu2csr_pc_curr_i != csr_mepc))         ^~~~~~~                                                
%Error: scr1/src/core/pipeline/scr1_pipe_csr.sv:1111: syntax error, unexpected |=>, expecting ')'                     ) |=>                                                             ^~~                                                       

riscv_isa march option is fixed even when changing ARCH

At line 4 in the makefile of riscv_isa test
I can see that it is fixed with IMF as march for toolchain.
Will it affect the test result when i setup test for CFG=BASE (RV32IC)?

Unaligned data access exceptions are not reported in simulation

Hello. I used the option TRACE=1 to enable tracelog generation. The simulated program carried out an unaligned data access. However, no exception was reported in the log file.

The unaligned data access was forced using this code:

`
#define untyped_address(x) ((void )(&x))
#define skewed_address(x) (untyped_address(x)+sizeof(x)-1)
#define alien_address(x) ((typeof(x))skewed_address(x))
#define alien_format(x) (*alien_address(x))

int main()
{
int fails=0;
int32_t mytable[8],myvar,A;
int32_t* puntero;
uint32_t B;
uint8_t i;
myvar=0x12345678;

//enable_AEBO;

puntero=alien_address(mytable[4]);
sc_printf("%x\n", puntero);
*puntero=myvar;
sc_printf("%x\n", *puntero);

//unaligned data access above
`

Compliance_breakpoint test failed when I disable breakpoint module

In breakpoint.S of riscv-compliance, csrw tselect, x0 will cause illegal instruction exception when the breakpoint module is disabled.
I think the exception is correct because the tselect CSR isn't implemented in such configuration.
Skipping the breakpoint test file in scr1_top_tb_ahb.sv (axi is similiar) is an easy method.

`ifndef SCR1_BRKM_EN
    if (~is_compliance(test_file) || get_ref_filename(test_file) != "breakpoint") begin
`endif // SCR1_BRKM_EN
        i_memory_tb.test_file = test_file;
        i_memory_tb.test_file_init = 1'b1;
        $write("\033[0;34m---Test: %s\033[0m\n", test_file);
        test_running <= 1'b1;
        rst_init <= 1'b1;
`ifndef SCR1_BRKM_EN
    end
`endif // SCR1_BRKM_EN

I didn't add string comparison of Verilator's version in above code.

I customize scr1_arch_description.svh but lots of assertion errors appear

below snapshot shows the differences between my own svh file (on the left) and the orignal svh file in scr1 github code.

The failed assertions are all about SCR1_SVA_IFU_DRC_UNDERFLOW,
But the assertion failures aren't reported if I use one of the three recommended configurations. (tried SCR1_CFG_RV32IC_BASE or SCR1_CFG_RV32EC_MIN)

Could you please give me some advices or comments? Thanks you very much.

pipeline info

Does this core support pipelining, stalling and flushing?

thanks

Invalid result of `DIV` operation

Hello!

While testing the iALU module, I encountered an incorrect result from the DIV operation. The expected result of signed integer division (operand 1 is 0xAAAA_AAAA, operand 2 is 0x5555_5555) is 2, but iALU produces 0xFFFF_FFFF.

Waveforms:

Example to reproduce (cocotb):

from typing import Any

import cocotb
from cocotb.clock import Clock
from cocotb.runner import get_runner
from cocotb.triggers import FallingEdge


@cocotb.test()
async def example_test(dut: Any):
    cocotb.start_soon(Clock(dut.clk, 2).start(start_high=False))

    await FallingEdge(dut.clk)
    await FallingEdge(dut.clk)

    # Reset

    dut.rst_n.value = 0
    dut.exu2ialu_main_op1_i.value = 0
    dut.exu2ialu_main_op2_i.value = 0
    dut.exu2ialu_cmd_i.value = 0  # SCR1_IALU_CMD_NONE
    dut.exu2ialu_rvm_cmd_vd_i.value = 0

    await FallingEdge(dut.clk)
    await FallingEdge(dut.clk)

    dut.rst_n.value = 1

    # Test

    OP1 = 0b10101010101010101010101010101010  # 0xAAAA_AAAA
    OP2 = 0b01010101010101010101010101010101  # 0x5555_5555

    dut.exu2ialu_main_op1_i.value = OP1
    dut.exu2ialu_main_op2_i.value = OP2
    dut.exu2ialu_cmd_i.value = 19  # SCR1_IALU_CMD_DIV
    dut.exu2ialu_rvm_cmd_vd_i.value = 1

    await FallingEdge(dut.clk)

    while dut.ialu2exu_rvm_res_rdy_o.value != 1:
        await FallingEdge(dut.clk)

    assert dut.ialu2exu_main_res_o == (
        OP1 // OP2
    )  # actual: `0xFFFF_FFFF`, expected: `2`


def run():
    runner = get_runner("verilator")

    runner.build(
        verilog_sources=["src/core/pipeline/scr1_pipe_ialu.sv"],
        includes=["src/includes"],
        hdl_toplevel="scr1_pipe_ialu",
        build_args=["-Wno-WIDTHEXPAND", "-Wno-CASEINCOMPLETE", "--trace"],
    )

    runner.test(hdl_toplevel="scr1_pipe_ialu", test_module="example")


if __name__ == "__main__":
    run()

---

• OS: Fedora 38
• Verilator 5.016 2023-09-16 rev v5.014-149-g57c816f90
• Python 3.11.4
• cocotb 1.8.0

error when running : make run_ncsim BUS=AMBA

Hi I am seeing following issue when running command : make run_ncsim BUS=AMBA
into directory /scr1 -

SCR bootloader’s banner does not show up after I RESET the Arty A7-100T board.

Hi,

I am trying to use the SCR1 SDK on Arty A7-100T board and was following the instructions given by arty_scr1_guide_en.pdf.
I can flash the memory with the part S25FL127S (refer to 3. FPGA Configuration Flash Programming). The DONE LED is on when flashing the ROM, and it is still on when the flash progress is done.
After I press the PROG button, the DONE LED becomes off and never come back to on state unless I reflash the ROM. I also did not receive the banner message as described in section 4 when the flash is done, no matter I press the PROG nor RESET buttons after flashing the ROM. (nothing was received in the serial terminal)

What could be wrong? Thank you. :-)

Assertions behavior, while reset, is incorrect

After every CPU reset (after end one test in series and start another) in ncsim console I see:

ncsim: *E,ASRTST (../src/pipeline/scr1_pipe_csr.sv,896): (time 132525 NS) Assertion scr1_top_tb.i_top.i_core_top.i_pipe_top.i_pipe_csr.SCR1_SVA_CSR_CYCLE_INC has failed
CSR Error: CYCLE increment wrong behavior
ncsim: *E,ASRTST (../src/pipeline/scr1_pipe_csr.sv,860): (time 132525 NS) Assertion scr1_top_tb.i_top.i_core_top.i_pipe_top.i_pipe_csr.SCR1_SVA_CSR_TIME_INC has failed
CSR Error: TIME increment wrong behavior

Coremark testcase still failed after added #9 issue solution

Hello,
I am running the benchmark of coremark and found some errors after following the #9 and get the results below:
First, I try the command:
$make run_vcs CFG=CUSTOM BUS=AXI ARCH=I VECT_IRQ=0 IPIC=0 TCM=0 TARGETS="coremark" ITERATIONS=31000
and the iteration times doesn't changed (still Iterations=1 and shows the results as below).

So I directly change the iteration time in /coremark/makefile like below.

This time it does change, but was not the result I expected. How can I fix it to get the pass result?

Thank you!

Syntax error

Hello,

I did the "make" and face multiple errors related to the "Behavior check".

I tried to comment these part, but of course, the design failed in Testing as follow.

I have also searched for the problem there was a few solutions on the internet, but non of them work.
Can you please help me to solve this?

Thank you in advance

syntax error on scr1_timer.sv

it seems syntax error on following lines,

scr1_timer.sv:#16
input type_scr1_mem_cmd_e dmem_cmd,

Solution:
add include file before module is defined,

`include "scr1_memif.svh"

Coremark test.

Hi,
I did all the steps and type:
make run_verilator BUS=AXI ARCH=IM IPIC=0
ISA is pass, Dhrystone is pass.
But the Coremark test seems kind of odd ! The partial message as follow: (in Line 363)

358 CoreMark 1.0
359 2K performance run parameters for coremark.
360 CoreMark Size : 666
361 Total ticks : 3533
362 Total time (secs): 0
363 ERROR! Must execute for at least 10 secs for a valid result!
364 Iterations : 1
365 Compiler version : GCC7.1.1 20170509
366 Compiler flags : -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las
367 Memory location : STATIC
368 seedcrc : 0xe9f5
369 [0]crclist : 0xe714
370 [0]crcmatrix : 0x1fd7
371 [0]crcstate : 0x8e3a
372 [0]crcfinal : 0xe714
373 Errors detected
374 ^[[0;32mTest passed^[[0m

Can someone help to solve this ? Many thanks.

Jason Lee

RV32E mode - assertions implement with errors

In RV32E mode, when define SCR1_RVE_EXT, tests can't be completted.

In file "scr1_pipe_csr.sv" signal "instret_nexc" not protected by SCR1_CSR_REDUCED_CNT, in some of assertions

Removing unprotected assertions don't let pass the tests anyway, simulation hangs...

Syntacore custom modification problems

Hello,
I have taken bare SCR1 core, then add my own RAM and ROM and create wishbone wrapper in order to use wishbone as a communication BUS. I have also generated .memh files with my soft for every extension I needed and load it to ROM. Also instantiate some necessary defines in my tb. But I have some problem with instruction receiving from ROM. PC stucks in 0x1C0 value immediately after first instruction request. I attached some screenshots of my defines, .memh file and waveforms with stucked PC

As you can see on screenshot below, boot addr started from 0x80, so I changed SCR1_ARCH_RST_VECTOR = 0x80.

To summarize, I can read first instruction from ROM but PC stucks even before cpu2mem request.

Could you please advise me something, probably I forgot to instantiate some defines or so?

Will there be any plan for adding the cache module in the core later?

Will there be any plan for adding the cache module in the core later?

Issues with 'make' and scr1 installation, errors with stdio.h, string.h, and sc_print.o and dhrystone21

Hello,

I am relatively new to everything, however, I have been trying to get the SCR1 installation up and running to test the simulations but continue to get errors and issues. I am currently running everything on the WSL Ubuntu for Windows using Docker Desktop and Verilator (v4.222 and have tried v4.102) but I cannot successful make the environment. I used the pre-built binary tools to install the toolchain. Below are the current errors I am getting, are there any suggestions?

Thank you!

Failing Tests With Verilator 4.034

If I use Verilator 4.034 (built from source) to run the hello test with AHB IMC the test fails:

scr1_top_tb_ahb
---Test:                       hello.hex

%Error: hello.hex
:0: $readmem file not found

I can see that the hello.hex is present in the build folder.

If I instead use the Verilator 4.010 that is packaged with Debian the test passes.

Incorrect linker flags' order into make file

I tried to build version 2023.09 but the test "dhrystone2" failed

Changes

Incorrect linker flags' order into make file

I tried to build version 2023.09 but the test "dhrystone2" failed

Changes

Error when running Dhrystone

Hello,
I get the following error when running Dhrystone:

I am using your Pre-built RISC-V GCC toolchain from http://syntacore.com/page/products/sw-tools.
At the same time, all other tests run without errors

Thank you!

Error: unrecognized opcode `fence.i'

I am trying to get the simulator working but when I run the make command I am met with the following issue:

/home/csmith/carter_scr1/sim/tests/riscv_isa/../../../dependencies/riscv-tests/isa/rv32ui/../rv64ui/fence_i.S:24: Error: unrecognized opcode fence.i' /home/csmith/carter_scr1/sim/tests/riscv_isa/../../../dependencies/riscv-tests/isa/rv32ui/../rv64ui/fence_i.S:37: Error: unrecognized opcode fence.i'

I am only learning how to set up all this stuff so I may have made a small error.

I cloned the scr1 GitHub onto my machine then copied over all of the files into my own personal GitHub. Once the files were all moved over I downloaded the GCC toolchain onto my machine and untarred it. I am using Ubuntu 22.04. Then I ran the command from the user manual: "git submodule update --init --recursive". I didn't know whether to run that command while in the original scr1 repository or while in my personal GitHub so I ran it in both.

One thing to add is that the error also shows up when I run the make command in the original scr1 repository.

According to the user manual, I should be able to simply run the make command while in my directory but I am met with the error above whenever I try to. Please let me know if you need any more info or if you have any solutions. Thanks for the help.

Benchmark simulation test

When i run coremark simulation test, it brings out no result.
There is only errors that said: test need to run longer than 10 seconds.
Do i need to set up anything else?
my run command: make run_vcs CFG=MAX TARGETS=coremark TRACE=1 SIM_BUILD_OPTS="-full64"

Theoretical value of tcm performance improvement

I would like to know how much the SCR1 core can improve with tcm function than without tcm function under the same compiler conditions. Is there a theoretical value, such as Dhrystone score comparison?

CDC issue ?

module scr1_tapc_synchronizer:

Unlike other inputs of domain sysCLK the input 'tapc2tapcsync_ch_tdo_i' (in the version which I work on currently: 'dmi_ch_tdo_core') is not two-staged synchronized to the output tapcsync2core_ch_tdo_o (formerly 'dmi_ch_tdo'). What is the rationale? STA complains about this path in my environment.

Thank you for help and clarification!

Issue with .sv files during make

I'm getting the following error during make :

%Error: /home/osboxes/scr1/src/core/pipeline/scr1_pipe_csr.sv:1094: syntax error, unexpected |=>, expecting ')'
e_mret |=> ($stable(csr_mepc_ff) & $stable(csr_mtval_ff))
^~~

how to modify tcm‘s address

We modified the tcm_mask and tcm_pattern of tcm to 32'hfffe0000 and 32'h00000000 respectively, so that the address of the tcm instruction is 32'h00000000 to 32'h0001ffff. However, during the actual operation,scr1 run for a while. , and the scr1 displays the x state.We wonder if we want to modify the address of tcm ,We only need to modify the tcm_mask and tcm_pattern.

Differences in executing instruction between configuration

At 6.2 in scr1_eas.pdf, you guys explained the main difference between configuration MAX, BASE, MINN is the insertion of instruction queue. Will this queue affect the clock cycle needed to execute one instruction between configurations?

Error running Coremark benchmark

Hi, I'm trying to run coremark benchmark but this error starts showing up. I'm using Verilator v4.102. The riscv_isa runs fine. May I know if there is something I need to do to run coremark? Thanks in advance :D

Core is hanging with disabling SCR1_DBG_EN (floating rst_n connectivity at scr1_pipe_top

We have noticed that SCR1 core is hanging when Simulated with disabling SCR1_DBG_EN switch

Our analysis shows the scr1_pipe_tdu reset signal (rst_n) is not driven when SCR1_DBG_EN disabled.

We feel this signal need to connect "pipe_rst_n"

Here is RTL Logic File: src/core/pipeline/scr1_pipe_top.sv

scr1_pipe_tdu i_pipe_tdu (
// Common signals
ifdef SCR1_DBG_EN .rst_n (dbg_rst_n ), else
.rst_n (rst_n ), <=== rst_n signal is floating
`endif // SCR1_DBG_EN

PULPissimo integration

I'm evaluating different RISC-V cores and I started with ones available for PULPissimo (ie. RI5CY and Ibex). Afterwards I've found out your project and thought that to make a fair performance comparison I could just use scr1 in PULPissimo.

I've written a wrapper to use with PULPissimo. Would you like me to push my changes to this repo and make scr1 an option in official PULPissimo repo?