AXI Interconnect problems

[syntacore]

AXI Interconnect problems

[a60626316]

I tried another method where the SCR1 and the memory's IMEM interface are directly connected, while the DMEM interfaces are all connected to the axi, as shown in the diagram below:

Additionally, I set the BASE_ADDR of the axi to 0. This allows the simulation to proceed smoothly. However, When I observe the waveform, I noticed that the instructions stop midway through execution. I'm not sure if there are additional settings that need to be configured?
orignal

modified

[achuykov-sc]

Hi @a60626316,

Could you please clarify a few things?

1. Could you confirm that CPU should not stop at that moment? For example, the WFI instruction halts the core
2. We have a timeout in default testbench. Please check that is not your case.

In any case, I'm proposing to check addresses and data on AXI to avoid reading wrong addresses or decode invalid instruction.

BR,
Alexander

[a60626316]

Hi, @achuykov-sc ,
Regarding the issue I mentioned in my second message, the stoppage was not due to a Timeout, but rather occurred while writing data to memory. However, after I reassembled each module and adjusted the parameters, it is now functioning normally, thank you.
Additionally, although I can currently operate using the second method, I would still like to inquire about the feasibility of using the first method of connection. If it is feasible, how should the AXI address be set? Thank you for your reply.

Best regards,
Jui