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achuykov-sc avatar achuykov-sc commented on May 22, 2024

Hi @shipherd,

Thanks for details but I have extra comments and questions for you?

  1. Please check that prebuild FPGA image is working for you: scr1-sdk/images/arty/scr1 at master · syntacore/scr1-sdk (github.com)
  2. If you build bitstream and MCS by yourself, could you please check that bitstream is working and after that switch to MCS
  3. Please make sure that you select SPI FLASH chip correctly. Unfortunately, different chips may be on board (S25FL127S or S25FL128S): https://files.digilent.com/resources/programmable-logic/documents/S25FL127S_PCN.pdf
  4. And I'm pretty sure, our document was written for A35t which is slightly different with A100t

Best regards,
Alexander

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shipherd avatar shipherd commented on May 22, 2024

Hi @achuykov-sc ,

  1. I was using the prebuild images. (which was cloned directly from the repository)
  2. Not using the self-build images.
  3. The SPI FLASH is labeled as shown below:
    image
  4. Have you tested them on A7-35t before ? (Not the old Arty 35t)

BTW, the part I chose:
image

Thank you :-)

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achuykov-sc avatar achuykov-sc commented on May 22, 2024

Hi @shipherd,

The scr1-arty-fpga.7z (https://github.com/syntacore/scr1-sdk/blob/master/images/arty/scr1/scr1-arty-fpga.7z) contains bitstream (aka arty_scr1_new.bit) in addition to MCS. Could you please try the bitstream (arty_scr1_new.bit) first without MCS programming?

Please note, the A100t is incompatible with A35t bitstream.

Best regards,
Alexander

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shipherd avatar shipherd commented on May 22, 2024

Hi @achuykov-sc ,

So, I am supposed to recompile everything for 100t board?

Thank you. :-)

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shipherd avatar shipherd commented on May 22, 2024

Hi @achuykov-sc,

I had recompiled the Block Design project and the banner came up.

Thank you for your help :-)

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