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2d-binary-content-addressable-memory-bcam

Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)

3d-cae

3d-convolutional-network

3d_nvm_tool

8-bit-deep-learning

Training neural networks with 8-bit computations

a2

aap-llvm

LLVM for An Altruistic Processor

aap-toolchain

Supporting scripts for the AAP tool chain

aap-verilog

Verilog implementation of AAP

acceleration

ACDA

accept

an approximate compiler

accept-apps

benchmarks for ACCEPT

ack

The Amsterdam Compiler Kit

activationfunctiondemo

The "Activation Function Demo" is a demo for implementing activation function with the mathod propsed in paper: Design Space Exploration of Neural Network Activation Function Circuits

adv_debug_sys

Advanced Debug System

aff3ct

A fast simulator and a library dedicated to the channel coding.

aladdin

A pre-RTL, power-performance model for fixed-function accelerators

altera-de2-ann

Artificial Neural Network on Altera DE2

analyze-spec-benchmarks

approx-vision

Designing image processing hardware and software for computer vision

approxbib

annotated bibliography on approximate computing

approxilyzer

A Systematic Framework for Instruction-Level Approximate Computing and its Application to Hardware Resiliency

arduino

FPGArduino

ariane

Ariane is a 6-stage RISC-V CPU

asfpp

ASF++ sources

asic-design

Digital signal processing that can minimize the bit-rate without degradation in the signal quality is highly desirable. In telecommunication, speech compression is one of the main application where low bit rate is desired to reduce the bandwidth requirement. As per Recommendation G.711: Pulse Code Modulation (PCM) of voice frequencies by International Telecommunication Union (ITU), the standard PCM signal bit rate is 64kbits/s. This project was developed based on, Recommendation G.726: 40, 32, 24, 16kbit/s Adaptive Differential Pulse Code Modulation (ADPCM) was used to achieve low bit rates for different application requirements. The design was targeted for processing 8 independent channels in a 125 microsecond frame. In order to achieve considerable reduction in system size and instantaneous power, the FMULT/ACCUM module in ADPCM algorithm was implemented as bit serial arithmetic operations with independent floating point multiplier and accumulator. A hierarchical bottom-up design and verification approach was followed resulting in gate level synthesis of MCAC, targeted to TSMC 0.18µm Process technology.

atlas

Atlas: Programming for Persistent Memory

audiocaffeinitial

developments on audio applications of the Caffe framework

automata-to-routing

awesome-deep-computation

A curated list of Deep Learning hardware, cycle/memory optimisation techniques